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build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names.

This commit is contained in:
Florent Kermarrec 2024-09-26 10:37:54 +02:00
parent a3a55fc8fb
commit 39d292a3c7
1 changed files with 16 additions and 15 deletions
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31
litex/build/efinix/common.py
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@ -35,13 +35,8 @@ if _have_colorama:
# Helpers ------------------------------------------------------------------------------------------ # Helpers ------------------------------------------------------------------------------------------
def _to_signal(obj): def assert_is_signal_or_clocksignal(obj):
if isinstance(obj, str): assert isinstance(obj, (ClockSignal, Signal)), f"Object {obj} is not a ClockSignal or Signal"
return ClockSignal(obj)
elif isinstance(obj, Signal):
return obj
else:
raise ValueError
# Efinix AsyncResetSynchronizer -------------------------------------------------------------------- # Efinix AsyncResetSynchronizer --------------------------------------------------------------------
@ -114,12 +109,13 @@ class EfinixClkInput(Module):
class EfinixClkOutputImpl(Module): class EfinixClkOutputImpl(Module):
def __init__(self, platform, i, o): def __init__(self, platform, i, o):
assert_is_signal_or_clocksignal(i)
block = { block = {
"type" : "GPIO", "type" : "GPIO",
"size" : 1, "size" : 1,
"location" : platform.get_pin_location(o)[0], "location" : platform.get_pin_location(o)[0],
"properties" : platform.get_pin_properties(o), "properties" : platform.get_pin_properties(o),
"name" : _to_signal(i), "name" : i,
"mode" : "OUTPUT_CLK", "mode" : "OUTPUT_CLK",
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)
@ -278,6 +274,7 @@ class EfinixDifferentialInput:
class EfinixDDRTristateImpl(Module): class EfinixDDRTristateImpl(Module):
def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk): def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk):
assert oe1 == oe2 assert oe1 == oe2
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(io) io_name = platform.get_pin_name(io)
io_pad = platform.get_pin_location(io) io_pad = platform.get_pin_location(io)
io_prop = platform.get_pin_properties(io) io_prop = platform.get_pin_properties(io)
@ -300,9 +297,9 @@ class EfinixDDRTristateImpl(Module):
"properties" : io_prop, "properties" : io_prop,
"size" : 1, "size" : 1,
"in_reg" : "DDIO_RESYNC", "in_reg" : "DDIO_RESYNC",
"in_clk_pin" : _to_signal(clk), "in_clk_pin" : clk,
"out_reg" : "DDIO_RESYNC", "out_reg" : "DDIO_RESYNC",
"out_clk_pin" : _to_signal(clk), "out_clk_pin" : clk,
"oe_reg" : "REG", "oe_reg" : "REG",
"is_inclk_inverted" : False, "is_inclk_inverted" : False,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
@ -319,6 +316,7 @@ class EfinixDDRTristate:
class EfinixSDRTristateImpl(EfinixDDRTristateImpl): class EfinixSDRTristateImpl(EfinixDDRTristateImpl):
def __init__(self, platform, io, o, oe, i, clk): def __init__(self, platform, io, o, oe, i, clk):
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(io) io_name = platform.get_pin_name(io)
io_pad = platform.get_pin_location(io) io_pad = platform.get_pin_location(io)
io_prop = platform.get_pin_properties(io) io_prop = platform.get_pin_properties(io)
@ -337,9 +335,9 @@ class EfinixSDRTristateImpl(EfinixDDRTristateImpl):
"properties" : io_prop, "properties" : io_prop,
"size" : 1, "size" : 1,
"in_reg" : "REG", "in_reg" : "REG",
"in_clk_pin" : _to_signal(clk), "in_clk_pin" : clk,
"out_reg" : "REG", "out_reg" : "REG",
"out_clk_pin" : _to_signal(clk), "out_clk_pin" : clk,
"oe_reg" : "REG", "oe_reg" : "REG",
"is_inclk_inverted" : False, "is_inclk_inverted" : False,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
@ -357,6 +355,7 @@ class EfinixSDRTristate(Module):
class EfinixSDROutputImpl(Module): class EfinixSDROutputImpl(Module):
def __init__(self, platform, i, o, clk): def __init__(self, platform, i, o, clk):
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(o) io_name = platform.get_pin_name(o)
io_pad = platform.get_pin_location(o) io_pad = platform.get_pin_location(o)
io_prop = platform.get_pin_properties(o) io_prop = platform.get_pin_properties(o)
@ -371,7 +370,7 @@ class EfinixSDROutputImpl(Module):
"properties" : io_prop, "properties" : io_prop,
"size" : 1, "size" : 1,
"out_reg" : "REG", "out_reg" : "REG",
"out_clk_pin" : _to_signal(clk), "out_clk_pin" : clk,
"is_inclk_inverted" : False, "is_inclk_inverted" : False,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
} }
@ -389,6 +388,7 @@ class EfinixSDROutput(Module):
class EfinixDDROutputImpl(Module): class EfinixDDROutputImpl(Module):
def __init__(self, platform, i1, i2, o, clk): def __init__(self, platform, i1, i2, o, clk):
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(o) io_name = platform.get_pin_name(o)
io_pad = platform.get_pin_location(o) io_pad = platform.get_pin_location(o)
io_prop = platform.get_pin_properties(o) io_prop = platform.get_pin_properties(o)
@ -405,7 +405,7 @@ class EfinixDDROutputImpl(Module):
"properties" : io_prop, "properties" : io_prop,
"size" : 1, "size" : 1,
"out_reg" : "DDIO_RESYNC", "out_reg" : "DDIO_RESYNC",
"out_clk_pin" : _to_signal(clk), "out_clk_pin" : clk,
"is_inclk_inverted" : False, "is_inclk_inverted" : False,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
} }
@ -421,6 +421,7 @@ class EfinixDDROutput:
class EfinixDDRInputImpl(Module): class EfinixDDRInputImpl(Module):
def __init__(self, platform, i, o1, o2, clk): def __init__(self, platform, i, o1, o2, clk):
assert_is_signal_or_clocksignal(clk)
io_name = platform.get_pin_name(i) io_name = platform.get_pin_name(i)
io_pad = platform.get_pin_location(i) io_pad = platform.get_pin_location(i)
io_prop = platform.get_pin_properties(i) io_prop = platform.get_pin_properties(i)
@ -436,7 +437,7 @@ class EfinixDDRInputImpl(Module):
"properties" : io_prop, "properties" : io_prop,
"size" : 1, "size" : 1,
"in_reg" : "DDIO_RESYNC", "in_reg" : "DDIO_RESYNC",
"in_clk_pin" : _to_signal(clk), "in_clk_pin" : clk,
"is_inclk_inverted" : False "is_inclk_inverted" : False
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)