VGA framebuffer connections
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parent
59f4490630
commit
3a02524cc7
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@ -6,5 +6,6 @@
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#define ID_BASE 0xe0001000
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#define TIMER0_BASE 0xe0001800
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#define MINIMAC_BASE 0xe0002000
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#define FB_BASE 0xe0002800
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#endif /* __CSRBASE_H */
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@ -1,5 +1,5 @@
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class Constraints:
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def __init__(self, crg0, norflash0, uart0, ddrphy0, minimac0):
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def __init__(self, crg0, norflash0, uart0, ddrphy0, minimac0, fb0):
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self.constraints = []
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def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
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self.constraints.append((signal, vec, pin, iostandard, extra))
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@ -16,6 +16,7 @@ class Constraints:
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add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
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add(crg0.trigger_reset, "AA4")
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add(crg0.phy_clk, "M20")
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add(crg0.vga_clk_pad, "A11")
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add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
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"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
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@ -61,6 +62,13 @@ class Constraints:
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add(minimac0.phy_col, "W20")
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add(minimac0.phy_crs, "W22")
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add_vec(fb0.vga_r, ["C6", "B6", "A6", "C7", "A7", "B8", "A8", "D9"])
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add_vec(fb0.vga_g, ["C8", "C9", "A9", "D7", "D8", "D10", "C10", "B10"])
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add_vec(fb0.vga_b, ["D11", "C12", "B12", "A12", "C13", "A13", "D14", "C14"])
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add(fb0.vga_hsync_n, "A14")
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add(fb0.vga_vsync_n, "C15")
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add(fb0.vga_psave_n, "B14")
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self._phy_rx_clk = minimac0.phy_rx_clk
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self._phy_tx_clk = minimac0.phy_tx_clk
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@ -0,0 +1,19 @@
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from migen.fhdl.structure import *
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class Framebuffer:
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def __init__(self, csr_address, asmiport):
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# VGA clock input
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self.vga_clk = Signal()
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# pads
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self.vga_psave_n = Signal()
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self.vga_hsync_n = Signal()
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self.vga_vsync_n = Signal()
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self.vga_sync_n = Signal()
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self.vga_blank_n = Signal()
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self.vga_r = Signal(BV(8))
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self.vga_g = Signal(BV(8))
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self.vga_b = Signal(BV(8))
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def get_fragment(self):
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return Fragment()
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@ -19,7 +19,9 @@ class M1CRG:
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"clk4x_wr_strb",
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"clk4x_rd",
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"clk4x_rd_strb",
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"phy_clk"
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"phy_clk",
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"vga_clk",
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"vga_clk_pad"
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]:
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s = Signal(name=name)
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setattr(self, name, s)
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18
top.py
18
top.py
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@ -5,7 +5,8 @@ from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
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from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, identifier, timer, minimac3
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from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
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identifier, timer, minimac3, framebuffer
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from cmacros import get_macros
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from constraints import Constraints
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@ -75,6 +76,7 @@ def get():
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#
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asmicon0 = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
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asmiport_wb = asmicon0.hub.get_port()
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asmiport_fb = asmicon0.hub.get_port()
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asmicon0.finalize()
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#
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@ -122,12 +124,14 @@ def get():
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uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
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identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version, int(clk_freq))
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timer0 = timer.Timer(csr_offset("TIMER0"))
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fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
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csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
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uart0.bank.interface,
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dfii0.bank.interface,
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identifier0.bank.interface,
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timer0.bank.interface,
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minimac0.bank.interface
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minimac0.bank.interface,
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#fb0.bank.interface
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])
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#
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@ -144,8 +148,14 @@ def get():
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#
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crg0 = m1crg.M1CRG(50*MHz, clk_freq)
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frag = autofragment.from_local() + interrupts + ddrphy_clocking(crg0, ddrphy0)
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cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0)
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vga_clocking = Fragment([
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fb0.vga_clk.eq(crg0.vga_clk)
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])
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frag = autofragment.from_local() \
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+ interrupts \
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+ ddrphy_clocking(crg0, ddrphy0) \
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+ vga_clocking
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cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0, fb0)
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src_verilog, vns = verilog.convert(frag,
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cst.get_ios(),
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name="soc",
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@ -23,7 +23,11 @@ module m1crg #(
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output clk4x_rd_strb,
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/* Ethernet PHY clock */
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output reg phy_clk
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output reg phy_clk, /* < unbuffered, to I/O */
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/* VGA clock */
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output vga_clk, /* < buffered, to internal clock network */
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output vga_clk_pad /* < forwarded through ODDR2, to I/O */
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);
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/*
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@ -190,5 +194,45 @@ BUFG bufg_x1(
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/* Ethernet PHY */
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always @(posedge pllout4)
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phy_clk <= ~phy_clk;
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/* VGA clock */
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// TODO: hook up the reprogramming interface
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DCM_CLKGEN #(
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.CLKFXDV_DIVIDE(2),
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.CLKFX_DIVIDE(4),
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.CLKFX_MD_MAX(2.0),
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.CLKFX_MULTIPLY(2),
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.CLKIN_PERIOD(0.0),
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.SPREAD_SPECTRUM("NONE"),
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.STARTUP_WAIT("FALSE")
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) vga_clock_gen (
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.CLKFX(vga_clk),
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.CLKFX180(),
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.CLKFXDV(),
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.LOCKED(),
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.PROGDONE(),
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.STATUS(),
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.CLKIN(pllout4),
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.FREEZEDCM(1'b0),
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.PROGCLK(1'b0),
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.PROGDATA(),
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.PROGEN(1'b0),
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.RST(1'b0)
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);
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ODDR2 #(
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.DDR_ALIGNMENT("NONE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) vga_clock_forward (
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.Q(vga_clk_pad),
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.C0(vga_clk),
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.C1(~vga_clk),
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.CE(1'b1),
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.D0(1'b1),
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.D1(1'b0),
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.R(1'b0),
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.S(1'b0)
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);
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endmodule
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