Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

.gitmodules: use our VexRiscv-verilog

This commit is contained in:
Florent Kermarrec 2019-04-26 23:49:06 +02:00
parent 78c09125be
commit 3a2e283613
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitmodules vendored
View File

@ -15,4 +15,4 @@
url = https://github.com/enjoy-digital/tapcfg
[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
path = litex/soc/cores/cpu/vexriscv/verilog
url = https://github.com/m-labs/VexRiscv-verilog.git
url = https://github.com/enjoy-digital/VexRiscv-verilog.git

2
litex/soc/cores/cpu/vexriscv/verilog

@ -1 +1 @@
Subproject commit ebe4064653bc143bf92a0ccdd1099173620fcbf5
Subproject commit 66faa6ece6551abac424146f9a27960ba10f4cf8