soc/interconnect/stream: add Cast and others small fixes

litex/soc/integration/soc_core.py

@@ -195,6 +195,7 @@ class SoCCore(Module):
             self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
 
         # Interrupts
+        if hasattr(self.cpu_or_bridge, "interrupt"):
             for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
                 if hasattr(self, k):
                     self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)

litex/soc/interconnect/stream.py

@@ -161,6 +161,12 @@ class Demultiplexer(Module):
 from copy import copy
 from litex.gen.util.misc import xdir
 
+def _rawbits_layout(l):
+    if isinstance(l, int):
+        return [("rawbits", l)]
+    else:
+        return l
+
 def pack_layout(l, n):
     return [("chunk"+str(i), l) for i in range(n)]
 
@@ -256,6 +262,26 @@ class Buffer(PipelinedActor):
                 self.q.param.eq(self.d.param)
             )
 
+
+class Cast(CombinatorialActor):
+    def __init__(self, layout_from, layout_to, reverse_from=False, reverse_to=False):
+        self.sink = Sink(_rawbits_layout(layout_from))
+        self.source = Source(_rawbits_layout(layout_to))
+        CombinatorialActor.__init__(self)
+
+        # # #
+
+        sigs_from = self.sink.payload.flatten()
+        if reverse_from:
+            sigs_from = list(reversed(sigs_from))
+        sigs_to = self.source.payload.flatten()
+        if reverse_to:
+            sigs_to = list(reversed(sigs_to))
+        if sum(len(s) for s in sigs_from) != sum(len(s) for s in sigs_to):
+            raise TypeError
+        self.comb += Cat(*sigs_to).eq(Cat(*sigs_from))
+
+
 class Unpack(Module):
     def __init__(self, n, layout_to, reverse=False):
         self.source = source = Source(layout_to)

litex/soc/interconnect/wishbonebridge.py

@@ -56,7 +56,7 @@ class WishboneStreamingBridge(Module):
             )
         ]
 
-        fsm = InsertReset(FSM(reset_state="IDLE"))
+        fsm = ResetInserter()(FSM(reset_state="IDLE"))
         timer = WaitTimer(clk_freq//10)
         self.submodules += fsm, timer
         self.comb += [