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fhdl/memory: Prefix memory files with build name. 

This simplify re-integrating pre-generated SubSoCs in a top level SoC.
This commit is contained in:
Florent Kermarrec 2022-05-06 20:21:30 +02:00
parent 7800858c7a
commit 3a388d1f19
2 changed files with 3 additions and 3 deletions
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4
litex/gen/fhdl/memory.py
View File

@ -13,7 +13,7 @@ from migen.fhdl.verilog import _printexpr as verilog_printexpr
from migen.fhdl.specials import * from migen.fhdl.specials import *
def memory_emit_verilog(memory, namespace, add_data_file): def memory_emit_verilog(name, memory, namespace, add_data_file):
# Helpers. # Helpers.
# -------- # --------
def gn(e): def gn(e):
@ -76,7 +76,7 @@ def memory_emit_verilog(memory, namespace, add_data_file):
formatter = f"{{:0{int(memory.width/4)}x}}\n" formatter = f"{{:0{int(memory.width/4)}x}}\n"
for d in memory.init: for d in memory.init:
content += formatter.format(d) content += formatter.format(d)
memory_filename = add_data_file(f"{gn(memory)}.init", content) memory_filename = add_data_file(f"{name}_{gn(memory)}.init", content)
r += "initial begin\n" r += "initial begin\n"
r += f"\t$readmemh(\"{memory_filename}\", {gn(memory)});\n" r += f"\t$readmemh(\"{memory_filename}\", {gn(memory)});\n"

2
litex/gen/fhdl/verilog.py
View File

@ -500,7 +500,7 @@ def _print_specials(name, overrides, specials, namespace, add_data_file, attr_tr
# Replace Migen Memory's emit_verilog with LiteX's implementation. # Replace Migen Memory's emit_verilog with LiteX's implementation.
if isinstance(special, Memory): if isinstance(special, Memory):
from litex.gen.fhdl.memory import memory_emit_verilog from litex.gen.fhdl.memory import memory_emit_verilog
pr = memory_emit_verilog(special, namespace, add_data_file) pr = memory_emit_verilog(name, special, namespace, add_data_file)
else: else:
pr = call_special_classmethod(overrides, special, "emit_verilog", namespace, add_data_file) pr = call_special_classmethod(overrides, special, "emit_verilog", namespace, add_data_file)
if pr is None: if pr is None: