fhdl/memory: Prefix memory files with build name.

This simplify re-integrating pre-generated SubSoCs in a top level SoC.

litex/gen/fhdl/memory.py

@@ -13,7 +13,7 @@ from migen.fhdl.verilog import _printexpr as verilog_printexpr
 from migen.fhdl.specials import *
 
 
-def memory_emit_verilog(memory, namespace, add_data_file):
+def memory_emit_verilog(name, memory, namespace, add_data_file):
     # Helpers.
     # --------
     def gn(e):
@@ -76,7 +76,7 @@ def memory_emit_verilog(memory, namespace, add_data_file):
         formatter = f"{{:0{int(memory.width/4)}x}}\n"
         for d in memory.init:
             content += formatter.format(d)
-        memory_filename = add_data_file(f"{gn(memory)}.init", content)
+        memory_filename = add_data_file(f"{name}_{gn(memory)}.init", content)
 
         r += "initial begin\n"
         r += f"\t$readmemh(\"{memory_filename}\", {gn(memory)});\n"

litex/gen/fhdl/verilog.py

@@ -500,7 +500,7 @@ def _print_specials(name, overrides, specials, namespace, add_data_file, attr_tr
         # Replace Migen Memory's emit_verilog with LiteX's implementation.
         if isinstance(special, Memory):
             from litex.gen.fhdl.memory import memory_emit_verilog
-            pr = memory_emit_verilog(special, namespace, add_data_file)
+            pr = memory_emit_verilog(name, special, namespace, add_data_file)
         else:
             pr = call_special_classmethod(overrides, special, "emit_verilog", namespace, add_data_file)
         if pr is None: