Merge pull request #121 from cr1901/patch-3

Update vivado.py
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Tim Ansell 2018-10-29 20:54:23 -07:00 committed by GitHub
commit 3a8bb94ab4
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@ -243,11 +243,8 @@ class XilinxVivadoToolchain:
if run:
if synth_mode == "yosys":
common._run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
else:
raise OSError("Error!")
_run_vivado(build_name, toolchain_path, source)
os.chdir(cwd)
return v_output.ns