commit
3a8bb94ab4
|
@ -243,11 +243,8 @@ class XilinxVivadoToolchain:
|
|||
if run:
|
||||
if synth_mode == "yosys":
|
||||
common._run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
|
||||
else:
|
||||
raise OSError("Error!")
|
||||
_run_vivado(build_name, toolchain_path, source)
|
||||
|
||||
|
||||
os.chdir(cwd)
|
||||
|
||||
return v_output.ns
|
||||
|
|
Loading…
Reference in New Issue