framebuffer: switch to real DMA
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parent
ce82f188d0
commit
3add96212b
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@ -207,25 +207,6 @@ def sim_fifo_gen():
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yield t
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yield t
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print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"]))
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print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"]))
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class FakeDMA(Actor):
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def __init__(self, port):
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self.port = port
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super().__init__(
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("address", Sink, [("a", BV(self.port.hub.aw))]),
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("data", Source, [("d", BV(self.port.hub.dw))]))
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def get_fragment(self):
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pixel = Signal(BV(32))
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comb = [
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self.endpoints["address"].ack.eq(1),
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self.endpoints["data"].stb.eq(1),
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self.token("data").d.eq(Replicate(pixel, 4))
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]
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sync = [
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If(self.endpoints["data"].ack, pixel.eq(pixel + 1))
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]
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return Fragment(comb, sync)
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class Framebuffer:
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class Framebuffer:
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def __init__(self, address, asmiport, simulation=False):
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def __init__(self, address, asmiport, simulation=False):
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asmi_bits = asmiport.hub.aw
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asmi_bits = asmiport.hub.aw
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@ -237,8 +218,7 @@ class Framebuffer:
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fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
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fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
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adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits))
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adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits))
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adrbuffer = ActorNode(plumbing.Buffer)
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adrbuffer = ActorNode(plumbing.Buffer)
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#dma = ActorNode(dma_asmi.SequentialReader(asmiport))
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dma = ActorNode(dma_asmi.SequentialReader(asmiport))
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dma = ActorNode(FakeDMA(asmiport))
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cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
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cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
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unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
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unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
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vtg = ActorNode(VTG())
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vtg = ActorNode(VTG())
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