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Adding missing vexriscv CPU.
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@ -43,6 +43,7 @@ repos = [
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("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)),
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("litex-data-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)),
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("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)),
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("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)),
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]
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]
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repos = OrderedDict(repos)
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repos = OrderedDict(repos)
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