Adding missing vexriscv CPU.

This commit is contained in:
Tim 'mithro' Ansell 2020-02-23 14:54:07 -08:00
parent ac3fd794f9
commit 3ae4f8f2de

View file

@ -43,6 +43,7 @@ repos = [
("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)), ("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)),
("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)), ("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)),
("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)), ("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)),
("litex-data-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)),
("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)), ("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)),
] ]
repos = OrderedDict(repos) repos = OrderedDict(repos)