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mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented)

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This commit is contained in:
Florent Kermarrec 2015-03-18 18:54:22 +01:00
parent 5a9afee234
commit 3aee58f484
1 changed files with 2 additions and 0 deletions
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2
mibuild/lattice/diamond.py
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@ -40,6 +40,8 @@ def _build_lpf(named_sc, named_pc):
def _build_files(device, sources, vincpaths, build_name): def _build_files(device, sources, vincpaths, build_name):
tcl = [] tcl = []
tcl.append("prj_project new -name \"%s\" -impl \"implementation\" -dev %s -synthesis \"synplify\"" %(build_name, device)) tcl.append("prj_project new -name \"%s\" -impl \"implementation\" -dev %s -synthesis \"synplify\"" %(build_name, device))
for path in vincpaths:
tcl.append("prj_impl option {include path} {\"" + path.replace("\\", "/") + "\"}")
for filename, language in sources: for filename, language in sources:
tcl.append("prj_src add \"" + filename.replace("\\", "/") + "\"") tcl.append("prj_src add \"" + filename.replace("\\", "/") + "\"")
tcl.append("prj_run Synthesis -impl implementation -forceOne") tcl.append("prj_run Synthesis -impl implementation -forceOne")