Use new syntax

milkymist/clkfx/__init__.py

@@ -4,8 +4,8 @@ from migen.fhdl.structure import *
 
 class Inst:
 	def __init__(self, infreq, outfreq):
-		declare_signal(self, "clkin")
+		self.clkin = Signal()
-		declare_signal(self, "clkout")
+		self.clkout = Signal()
 		
 		ratio = Fraction(outfreq)/Fraction(infreq)
 		appr = ratio.limit_denominator(32)

milkymist/lm32/__init__.py

@@ -5,8 +5,8 @@ class Inst:
 	def __init__(self):
 		self.ibus = i = wishbone.Master("lm32i")
 		self.dbus = d = wishbone.Master("lm32d")
-		declare_signal(self, "interrupt", BV(32))
+		self.interrupt = Signal(BV(32))
-		declare_signal(self, "ext_break")
+		self.ext_break = Signal()
 		self._inst = Instance("lm32_top",
 			[("I_ADR_O", i.adr_o),
 			("I_DAT_O", i.dat_o),

milkymist/m1reset/__init__.py

@@ -1,15 +1,12 @@
-from functools import partial
-
 from migen.fhdl.structure import *
 
 class Inst:
 	def __init__(self):
-		d = partial(declare_signal, self)
+		self.trigger_reset = Signal()
-		d("trigger_reset")
+		self.sys_rst = Signal()
-		d("sys_rst")
+		self.ac97_rst_n = Signal()
-		d("ac97_rst_n")
+		self.videoin_rst_n = Signal()
-		d("videoin_rst_n")
+		self.flash_rst_n = Signal()
-		d("flash_rst_n")
 		self._inst = Instance("m1reset",
 			[("sys_rst", self.sys_rst),
 			("ac97_rst_n", self.ac97_rst_n),

milkymist/norflash/__init__.py

@@ -1,5 +1,3 @@
-from functools import partial
-
 from migen.fhdl.structure import *
 from migen.bus import wishbone
 from migen.corelogic import timeline
@@ -7,12 +5,11 @@ from migen.corelogic import timeline
 class Inst:
 	def __init__(self, adr_width, rd_timing):
 		self.bus = wishbone.Slave("norflash")
-		d = partial(declare_signal, self)
+		self.adr = Signal(BV(adr_width-1))
-		d("adr", BV(adr_width-1))
+		self.d = Signal(BV(16))
-		d("d", BV(16))
+		self.oe_n = Signal()
-		d("oe_n")
+		self.we_n = Signal()
-		d("we_n")
+		self.ce_n = Signal()
-		d("ce_n")
 		self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
 			[(0, [self.adr.eq(Cat(0, self.bus.adr_i[2:adr_width]))]),
 			(rd_timing, [

milkymist/uart/__init__.py

@@ -1,5 +1,3 @@
-from functools import partial
-
 from migen.fhdl.structure import *
 from migen.bank.description import *
 from migen.bank import csrgen
@@ -13,44 +11,54 @@ class Inst:
 		self._f_thre = Field(stat, "thre", access_bus=READ_ONLY, access_dev=WRITE_ONLY)
 		
 		self.bank = csrgen.Bank([rxtx, divisor, stat], address=address)
-		d = partial(declare_signal, self)
+		self.tx = Signal(reset=1)
-		d("tx", reset=1)
+		self.rx = Signal()
-		d("rx")
 		
-		d("_enable16")
-		d("_enable16_counter", BV(16))
-		d("_tx_reg", BV(8))
-		d("_tx_bitcount", BV(4))
-		d("_tx_count16", BV(4))
-		d("_tx_busy")
 		self.divisor = int(clk_freq/baud/16); # TODO
 	
 	def get_fragment(self):
-		comb = [self._enable16.eq(self._enable16_counter == Constant(0, BV(16)))]
+		enable16 = Signal()
-		sync = [self._enable16_counter.eq(self._enable16_counter - 1),
+		enable16_counter = Signal(BV(16))
-			If(self._enable16, self._enable16_counter.eq(self.divisor - 1))] # TODO
+		comb = [
+			enable16.eq(enable16_counter == Constant(0, BV(16)))
+		]
+		sync = [
+			enable16_counter.eq(enable16_counter - 1),
+			If(enable16,
+				enable16_counter.eq(self.divisor - 1)) # TODO
+		]
 		
-		sync += [If(self._rxtx.dev_re,
+		tx_reg = Signal(BV(8))
-			self._tx_reg.eq(self._rxtx.dev_r),
+		tx_bitcount = Signal(BV(4))
-			self._tx_bitcount.eq(0),
+		tx_count16 = Signal(BV(4))
-			self._tx_count16.eq(1),
+		tx_busy = Signal()
-			self._tx_busy.eq(1),
+		sync += [
-			self.tx.eq(0)
+			If(self._rxtx.dev_re,
-		).Elif(self._enable16 & self._tx_busy,
+				tx_reg.eq(self._rxtx.dev_r),
-			self._tx_count16.eq(self._tx_count16 + 1),
+				tx_bitcount.eq(0),
-			If(self._tx_count16 == Constant(0, BV(4)),
+				tx_count16.eq(1),
-				self._tx_bitcount.eq(self._tx_bitcount + 1),
+				tx_busy.eq(1),
-				If(self._tx_bitcount == 8,
+				self.tx.eq(0)
-					self.tx.eq(1)
+			).Elif(enable16 & tx_busy,
-				).Elif(self._tx_bitcount == 9,
+				tx_count16.eq(tx_count16 + 1),
-					self.tx.eq(1),
+				If(tx_count16 == Constant(0, BV(4)),
-					self._tx_busy.eq(0)
+					tx_bitcount.eq(tx_bitcount + 1),
-				).Else(
+					If(tx_bitcount == 8,
-					self.tx.eq(self._tx_reg[0]),
+						self.tx.eq(1)
-					self._tx_reg.eq(Cat(self._tx_reg[1:], 0))
+					).Elif(tx_bitcount == 9,
+						self.tx.eq(1),
+						tx_busy.eq(0)
+					).Else(
+						self.tx.eq(tx_reg[0]),
+						tx_reg.eq(Cat(tx_reg[1:], 0))
+					)
 				)
 			)
-		)]
+		]
+		
+		comb += [
+			self._f_thre.dev_we.eq(1),
+			self._f_thre.dev_w.eq(~tx_busy)
+		]
 		
-		comb += [self._f_thre.dev_we.eq(1), self._f_thre.dev_w.eq(~self._tx_busy)]
 		return self.bank.get_fragment() + Fragment(comb, sync, pads={self.tx, self.rx})