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fhdl/verilog: Remove blocking_assign (not used with LiteX).

This commit is contained in:
Florent Kermarrec 2021-10-15 15:20:01 +02:00
parent fe2998a19c
commit 3b78fd928d
2 changed files with 10 additions and 26 deletions
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6
litex/build/sim/verilator.py
View File

@ -189,7 +189,6 @@ class SimVerilatorToolchain:
trace_fst = False,
trace_start = 0,
trace_end = -1,
regular_comb = False,
interactive = True,
pre_run_callback = None):
@ -205,10 +204,7 @@ class SimVerilatorToolchain:
platform.finalize(fragment)
# Generate verilog
v_output = platform.get_verilog(fragment,
name = build_name,
regular_comb = regular_comb,
blocking_assign = True)
v_output = platform.get_verilog(fragment, name=build_name)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)

30
litex/gen/fhdl/verilog.py
View File

@ -374,7 +374,7 @@ def _print_module(f, ios, name, ns, attr_translate):
# COMBINATORIAL LOGIC #
# ------------------------------------------------------------------------------------------------ #
def _print_combinatorial_logic_sim(f, ns, blocking_assign):
def _print_combinatorial_logic_sim(f, ns):
r = ""
if f.comb:
from collections import defaultdict
@ -394,17 +394,13 @@ def _print_combinatorial_logic_sim(f, ns, blocking_assign):
r += "assign " + _print_node(ns, _AT_BLOCKING, 0, stmts[0])
else:
r += "always @(*) begin\n"
if blocking_assign:
r += "\t" + ns.get_name(t) + " = " + _print_expression(ns, t.reset)[0] + ";\n"
r += _print_node(ns, _AT_BLOCKING, 1, stmts, t)
else:
r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
r += _print_node(ns, _AT_NONBLOCKING, 1, stmts, t)
r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
r += _print_node(ns, _AT_NONBLOCKING, 1, stmts, t)
r += "end\n"
r += "\n"
return r
def _print_combinatorial_logic_synth(f, ns, blocking_assign):
def _print_combinatorial_logic_synth(f, ns):
r = ""
if f.comb:
groups = group_by_targets(f.comb)
@ -414,14 +410,9 @@ def _print_combinatorial_logic_synth(f, ns, blocking_assign):
r += "assign " + _print_node(ns, _AT_BLOCKING, 0, g[1][0])
else:
r += "always @(*) begin\n"
if blocking_assign:
for t in g[0]:
r += "\t" + ns.get_name(t) + " = " + _print_expression(ns, t.reset)[0] + ";\n"
r += _print_node(ns, _AT_BLOCKING, 1, g[1])
else:
for t in g[0]:
r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
r += _print_node(ns, _AT_NONBLOCKING, 1, g[1])
for t in g[0]:
r += "\t" + ns.get_name(t) + " <= " + _print_expression(ns, t.reset)[0] + ";\n"
r += _print_node(ns, _AT_NONBLOCKING, 1, g[1])
r += "end\n"
r += "\n"
return r
@ -470,7 +461,6 @@ class DummyAttrTranslate(dict):
def convert(f, ios=set(), name="top",
special_overrides = dict(),
attr_translate = DummyAttrTranslate(),
blocking_assign = False,
regular_comb = True):
# Create ConvOutput.
@ -534,11 +524,9 @@ def convert(f, ios=set(), name="top",
# Combinatorial Logic.
if regular_comb:
verilog += _print_combinatorial_logic_synth(f, ns,
blocking_assign = blocking_assign
)
verilog += _print_combinatorial_logic_synth(f, ns)
else:
verilog += _print_combinatorial_logic_sim(f, ns, blocking_assign=blocking_assign)
verilog += _print_combinatorial_logic_sim(f, ns)
# Synchronous Logic.
verilog += _print_synchronous_logic(f, ns)