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wishbone.SRAM: Support non-32bit wishbone widths.

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Tim 'mithro' Ansell 2018-11-25 12:56:37 -08:00
parent bc173380f2
commit 3b9e4c4df6
1 changed files with 1 additions and 1 deletions
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2
litex/soc/interconnect/wishbone.py
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@ -651,7 +651,7 @@ class SRAM(Module):
# generate write enable signal # generate write enable signal
if not read_only: if not read_only:
self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i]) self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
for i in range(4)] for i in range(bus_data_width//8)]
# address and data # address and data
self.comb += [ self.comb += [
port.adr.eq(self.bus.adr[:len(port.adr)]), port.adr.eq(self.bus.adr[:len(port.adr)]),