sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
This commit is contained in:
Florent Kermarrec
parent
a1f7ecc8c5
commit
3b9f287bab
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@ -58,8 +58,8 @@ class _Bank(Module):
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class MiniconSettings:
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def __init__(self):
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pass
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def __init__(self, l2_size=0):
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self.l2_size = l2_size
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class Minicon(Module):
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@ -1,168 +1,49 @@
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.bank.description import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import split, displacer, chooser
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from migen.genlib.record import Record, layout_len
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# cachesize (in 32-bit words) is the size of the data store, must be a power of 2
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class WB2LASMI(Module, AutoCSR):
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def __init__(self, cachesize, lasmim):
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self._cachesize = CSRStatus(8, reset=log2_int(cachesize))
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self.wishbone = wishbone.Interface()
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class WB2LASMI(Module):
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def __init__(self, wishbone, lasmim):
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###
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data_width = flen(self.wishbone.dat_r)
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if lasmim.dw > data_width and (lasmim.dw % data_width) != 0:
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raise ValueError("LASMI data width must be a multiple of {dw}".format(dw=data_width))
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if lasmim.dw < data_width and (data_width % lasmim.dw) != 0:
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raise ValueError("WISHBONE data width must be a multiple of {dw}".format(dw=lasmim.dw))
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# Split address:
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# TAG | LINE NUMBER | LINE OFFSET
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offsetbits = log2_int(max(lasmim.dw//data_width, 1))
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addressbits = lasmim.aw + offsetbits
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linebits = log2_int(cachesize) - offsetbits
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tagbits = addressbits - linebits
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wordbits = log2_int(max(data_width//lasmim.dw, 1))
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adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
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word = Signal(wordbits) if wordbits else None
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# Data memory
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data_mem = Memory(lasmim.dw*2**wordbits, 2**linebits)
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data_port = data_mem.get_port(write_capable=True, we_granularity=8)
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self.specials += data_mem, data_port
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write_from_lasmi = Signal()
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write_to_lasmi = Signal()
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if adr_offset is None:
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adr_offset_r = None
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else:
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adr_offset_r = Signal(offsetbits)
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self.sync += adr_offset_r.eq(adr_offset)
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self.comb += [
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data_port.adr.eq(adr_line),
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If(write_from_lasmi,
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displacer(lasmim.dat_r, word, data_port.dat_w),
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displacer(Replicate(1, lasmim.dw//8), word, data_port.we)
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).Else(
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data_port.dat_w.eq(Replicate(self.wishbone.dat_w, max(lasmim.dw//data_width, 1))),
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If(self.wishbone.cyc & self.wishbone.stb & self.wishbone.we & self.wishbone.ack,
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displacer(self.wishbone.sel, adr_offset, data_port.we, 2**offsetbits, reverse=True)
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)
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),
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If(write_to_lasmi,
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chooser(data_port.dat_r, word, lasmim.dat_w),
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lasmim.dat_we.eq(2**(lasmim.dw//8)-1)
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),
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chooser(data_port.dat_r, adr_offset_r, self.wishbone.dat_r, reverse=True)
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]
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# Tag memory
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tag_layout = [("tag", tagbits), ("dirty", 1)]
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tag_mem = Memory(layout_len(tag_layout), 2**linebits)
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tag_port = tag_mem.get_port(write_capable=True)
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self.specials += tag_mem, tag_port
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tag_do = Record(tag_layout)
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tag_di = Record(tag_layout)
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self.comb += [
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tag_do.raw_bits().eq(tag_port.dat_r),
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tag_port.dat_w.eq(tag_di.raw_bits())
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]
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self.comb += [
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tag_port.adr.eq(adr_line),
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tag_di.tag.eq(adr_tag)
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]
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if word is not None:
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self.comb += lasmim.adr.eq(Cat(word, adr_line, tag_do.tag))
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else:
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self.comb += lasmim.adr.eq(Cat(adr_line, tag_do.tag))
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# Lasmim word computation, word_clr and word_inc will be simplified
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# at synthesis when wordbits=0
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word_clr = Signal()
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word_inc = Signal()
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if word is not None:
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self.sync += \
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If(word_clr,
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word.eq(0),
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).Elif(word_inc,
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word.eq(word+1)
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)
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def word_is_last(word):
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if word is not None:
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return word == 2**wordbits-1
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else:
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return 1
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# Control FSM
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assert(lasmim.write_latency >= 1 and lasmim.read_latency >= 1)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT"))
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If(wishbone.cyc & wishbone.stb,
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NextState("REQUEST")
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)
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fsm.act("TEST_HIT",
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word_clr.eq(1),
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If(tag_do.tag == adr_tag,
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self.wishbone.ack.eq(1),
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If(self.wishbone.we,
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tag_di.dirty.eq(1),
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tag_port.we.eq(1)
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)
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fsm.act("REQUEST",
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lasmim.stb.eq(1),
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lasmim.we.eq(wishbone.we),
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If(lasmim.req_ack,
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If(wishbone.we,
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NextState("WRITE_DATA")
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).Else(
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NextState("READ_DATA")
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)
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)
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)
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fsm.act("WRITE_DATA",
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If(lasmim.dat_w_ack,
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lasmim.dat_we.eq(wishbone.sel),
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wishbone.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("READ_DATA",
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If(lasmim.dat_r_ack,
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wishbone.ack.eq(1),
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NextState("IDLE")
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),
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NextState("IDLE")
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).Else(
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If(tag_do.dirty,
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NextState("EVICT_REQUEST")
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).Else(
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NextState("REFILL_WRTAG")
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)
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)
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)
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fsm.act("EVICT_REQUEST",
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lasmim.stb.eq(1),
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lasmim.we.eq(1),
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If(lasmim.req_ack, NextState("EVICT_DATA"))
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)
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fsm.act("EVICT_DATA",
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# Address / Datapath
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self.comb += [
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lasmim.adr.eq(wishbone.adr),
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If(lasmim.dat_w_ack,
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write_to_lasmi.eq(1),
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word_inc.eq(1),
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If(word_is_last(word),
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NextState("REFILL_WRTAG"),
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).Else(
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NextState("EVICT_REQUEST")
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)
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)
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)
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fsm.act("REFILL_WRTAG",
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# Write the tag first to set the LASMI address
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tag_port.we.eq(1),
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word_clr.eq(1),
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NextState("REFILL_REQUEST")
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)
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fsm.act("REFILL_REQUEST",
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lasmim.stb.eq(1),
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If(lasmim.req_ack, NextState("REFILL_DATA"))
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)
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fsm.act("REFILL_DATA",
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If(lasmim.dat_r_ack,
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write_from_lasmi.eq(1),
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word_inc.eq(1),
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If(word_is_last(word),
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NextState("TEST_HIT"),
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).Else(
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NextState("REFILL_REQUEST")
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)
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)
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)
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lasmim.dat_w.eq(wishbone.dat_w),
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),
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wishbone.dat_r.eq(lasmim.dat_r)
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]
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@ -12,7 +12,7 @@ from misoclib.soc import SoC
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class SDRAMSoC(SoC):
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csr_map = {
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"sdram": 8,
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"wishbone2lasmi": 9,
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"l2_cache": 9,
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"memtest_w": 10,
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"memtest_r": 11
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}
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@ -45,6 +45,7 @@ class SDRAMSoC(SoC):
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phy.module.geom_settings.colbits)*sdram_width//8
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# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
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main_ram_size = min(main_ram_size, 256*1024*1024)
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l2_size = self.sdram_controller_settings.l2_size
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# LASMICON frontend
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if isinstance(self.sdram_controller_settings, LASMIconSettings):
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@ -55,23 +56,39 @@ class SDRAMSoC(SoC):
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self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
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self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
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l2_size = self.sdram_controller_settings.l2_size
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if l2_size:
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sdram_bus = wishbone.Interface()
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lasmim = self.sdram.crossbar.get_master()
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l2_cache = wishbone.Cache(l2_size//4, sdram_bus, wishbone.Interface(lasmim.dw))
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# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
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# Remove this workaround when fixed by Xilinx.
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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from migen.fhdl.simplify import FullMemoryWE
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self.submodules.wishbone2lasmi = FullMemoryWE()(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
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self.submodules.l2_cache = FullMemoryWE()(l2_cache)
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else:
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())
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self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)
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self.submodules.l2_cache = l2_cache
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_cache.slave, lasmim)
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self.register_mem("main_ram", self.mem_map["main_ram"], sdram_bus, main_ram_size)
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# MINICON frontend
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elif isinstance(self.sdram_controller_settings, MiniconSettings):
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self.submodules.converter = wishbone.Converter(wishbone.Interface(), self.sdram.controller.bus)
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self.register_mem("main_ram", self.mem_map["main_ram"], self.converter.master, main_ram_size)
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sdram_bus = wishbone.Interface()
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if l2_size:
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l2_cache = wishbone.Cache(l2_size//4, sdram_bus, self.sdram.controller.bus)
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# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
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# Remove this workaround when fixed by Xilinx.
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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from migen.fhdl.simplify import FullMemoryWE
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self.submodules.l2_cache = FullMemoryWE()(l2_cache)
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else:
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self.submodules.l2_cache = l2_cache
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else:
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self.submodules.converter = wishbone.Converter(sdram_bus, self.sdram.controller.bus)
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self.register_mem("main_ram", self.mem_map["main_ram"], sdram_bus, main_ram_size)
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def do_finalize(self):
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if not self.integrated_main_ram_size:
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@ -67,7 +67,7 @@ void flush_cpu_dcache(void)
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#endif
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}
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#ifdef CSR_WISHBONE2LASMI_BASE
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#ifdef CSR_L2_CACHE_BASE
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void flush_l2_cache(void)
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{
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unsigned int l2_nwords;
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@ -75,7 +75,7 @@ void flush_l2_cache(void)
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register unsigned int addr;
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register unsigned int dummy;
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l2_nwords = 1 << wishbone2lasmi_cachesize_read();
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l2_nwords = 1 << l2_cache_size_read();
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for(i=0;i<2*l2_nwords;i++) {
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addr = MAIN_RAM_BASE + i*4;
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#if defined (__lm32__)
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