CHANGES.md: Update.
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- software/liblitespi : Fixed xor-used-pow bug (#2001).
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- soc : Fixed AHB2Wishbone bridge creation (#1998).
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- soc : Fixed parameters propagation for AXI data-width conversion (#1997).
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- soc/cores/clock/colognechip : Fixed and reworked locked signal handling.
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[> Added
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- build : Added initial Apicula (Gowin) Platform support (#2036).
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- build : Added initial Agilex5 support.
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- liteeth/mac : Improved broadcast filtering logic in Hybrid Mode (https://github.com/enjoy-digital/liteeth/pull/165).
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- soc/cores/hyperbus : Rewritten HyperRAM core to enhance performance and add new features (#2053).
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- litedram : Added bank_byte_alignement parameter for improvded address mapping (https://github.com/enjoy-digital/litedram/pull/360).
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[> Changed
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