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boards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE on SDRAM pins.

This commit is contained in:
Florent Kermarrec 2020-04-09 18:55:01 +02:00
parent 6c429c9995
commit 3c0ba8ae62
1 changed files with 35 additions and 15 deletions
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50
litex/boards/platforms/ulx3s.py
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@ -8,34 +8,54 @@ from litex.build.lattice import LatticePlatform
_io = [
("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")),
("rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
("rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("B2"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("C2"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("C1"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("D2"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("D1"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("E2"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("E1"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("H3"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("D1"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("E2"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("E1"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("H3"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
),
("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
("spisdcard", 0,
Subsignal("clk", Pins("J1")),
Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
),
("sdram_clock", 0, Pins("F19"),
Misc("PULLMODE=NONE"),
Misc("DRIVE=4"),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33")
),
("sdram", 0,
Subsignal("a", Pins("M20 M19 L20 L19 K20 K19 K18 J20 J19 H20 N19 G20 G19")),
Subsignal("dq", Pins("J16 L18 M18 N18 P18 T18 T17 U20 E19 D20 D19 C20 E18 F18 J18 J17")),
Subsignal("we_n", Pins("T20")),
Subsignal("a", Pins(
"M20 M19 L20 L19 K20 K19 K18 J20",
"J19 H20 N19 G20 G19")),
Subsignal("dq", Pins(
"J16 L18 M18 N18 P18 T18 T17 U20",
"E19 D20 D19 C20 E18 F18 J18 J17")),
Subsignal("we_n", Pins("T20")),
Subsignal("ras_n", Pins("R20")),
Subsignal("cas_n", Pins("T19")),
Subsignal("cs_n", Pins("P20")),
Subsignal("cke", Pins("F20")),
Subsignal("ba", Pins("P19 N20")),
Subsignal("dm", Pins("U19 E20")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
Subsignal("cs_n", Pins("P20")),
Subsignal("cke", Pins("F20")),
Subsignal("ba", Pins("P19 N20")),
Subsignal("dm", Pins("U19 E20")),
Misc("PULLMODE=NONE"),
Misc("DRIVE=4"),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")),
@ -68,7 +88,7 @@ _io = [
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk25"
default_clk_name = "clk25"
default_clk_period = 1e9/25e6
def __init__(self, device="LFE5U-45F", **kwargs):