build: Cosmetic cleanups.

This commit is contained in:
Florent Kermarrec 2022-08-05 08:22:17 +02:00
parent c2b62a6b0c
commit 3c1e8e74fc
24 changed files with 91 additions and 88 deletions

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@ -17,8 +17,7 @@ from litex.build.generic_platform import *
from litex.build.generic_toolchain import GenericToolchain
from litex.build import tools
# TangDinastyToolchain -----------------------------------------------------------------------------------
# TangDinastyToolchain -----------------------------------------------------------------------------
class TangDinastyToolchain(GenericToolchain):
attr_translate = {}

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@ -10,7 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.io import *
# Anlogic AsyncResetSynchronizer ---------------------------------------------------------------------
# Anlogic AsyncResetSynchronizer -------------------------------------------------------------------
class AnlogicAsyncResetSynchronizerImpl(Module):
def __init__(self, cd, async_reset):
@ -45,7 +45,7 @@ class AnlogicAsyncResetSynchronizer:
def lower(dr):
return AnlogicAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
# Anlogic Special Overrides --------------------------------------------------------------------------
# Anlogic Special Overrides ------------------------------------------------------------------------
anlogic_special_overrides = {
AsyncResetSynchronizer: AnlogicAsyncResetSynchronizer,

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@ -10,7 +10,7 @@ import os
from litex.build.generic_platform import GenericPlatform
from litex.build.anlogic import common, anlogic
# AnlogicPlatform -----------------------------------------------------------------------------------
# AnlogicPlatform ----------------------------------------------------------------------------------
class AnlogicPlatform(GenericPlatform):
bitstream_ext = ".fs"

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@ -57,7 +57,7 @@ class EfinityToolchain(GenericToolchain):
return GenericToolchain.build(self, platform, fragment, **kwargs)
# Timing Constraints (.sdc) ------------------------------------------------------------------------
# Timing Constraints (.sdc) --------------------------------------------------------------------
def build_timing_constraints(self, vns):
sdc = []
@ -87,7 +87,7 @@ class EfinityToolchain(GenericToolchain):
tools.write_to_file("{}.sdc".format(self._build_name), "\n".join(sdc))
return (self._build_name + ".sdc", "SDC")
# Peripheral configuration (.xml) ------------------------------------------------------------------
# Peripheral configuration (.xml) --------------------------------------------------------------
def get_pin_direction(self, pinname):
pins = self.platform.constraint_manager.get_io_signals()
@ -219,7 +219,7 @@ class EfinityToolchain(GenericToolchain):
# Project configuration (.xml) ---------------------------------------------------------------------
# Project configuration (.xml) -----------------------------------------------------------------
def build_project(self):
now = datetime.datetime.now()

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@ -5,13 +5,13 @@
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
import subprocess
from litex.build import tools
# Generic Programmer -------------------------------------------------------------------------------
class GenericProgrammer:
def __init__(self, flash_proxy_basename=None):

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@ -80,7 +80,7 @@ class GowinDifferentialInput:
def lower(dr):
return GowinDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
# Gowin Differential Output -------------------------------------------------------------------------
# Gowin Differential Output ------------------------------------------------------------------------
class GowinDifferentialOutputImpl(Module):
def __init__(self, i, o_p, o_n):

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@ -10,7 +10,7 @@ import os
from litex.build.generic_platform import GenericPlatform
from litex.build.gowin import common, gowin
# GowinPlatform -----------------------------------------------------------------------------------
# GowinPlatform ------------------------------------------------------------------------------------
class GowinPlatform(GenericPlatform):
bitstream_ext = ".fs"

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@ -11,7 +11,7 @@ from shutil import which
from litex.build.generic_programmer import GenericProgrammer
from litex.build import tools
# GowinProgrammer --------------------------------------------------------------------------------
# GowinProgrammer ----------------------------------------------------------------------------------
GOWIN_PMODE_SRAM = 4
GOWIN_PMODE_EMBFLASH = 5

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@ -298,7 +298,7 @@ class LatticeNXDDROutput:
def lower(dr):
return LatticeNXDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
# NX DDR Tristate ------------------------------------------------------------------------------------
# NX DDR Tristate ----------------------------------------------------------------------------------
class LatticeNXDDRTristateImpl(Module):
def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):

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@ -22,7 +22,7 @@ from litex.build.yosys_nextpnr_toolchain import YosysNextPNRToolchain
import math
# LatticeOxideToolchain --------------------------------------------------------------------------
# LatticeOxideToolchain ----------------------------------------------------------------------------
class LatticeOxideToolchain(YosysNextPNRToolchain):
attr_translate = {

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@ -24,7 +24,7 @@ class LatticeProgrammer(GenericProgrammer):
tools.write_to_file(xcf_file, xcf_content)
self.call(["pgrcmd", "-infile", xcf_file], check=False)
# OpenOCDJTAGProgrammer --------------------------------------------------------------------------------
# OpenOCDJTAGProgrammer ----------------------------------------------------------------------------
class OpenOCDJTAGProgrammer(GenericProgrammer):
def __init__(self, config, flash_proxy_basename=None):
@ -159,7 +159,7 @@ class UJProg(GenericProgrammer):
def load_bitstream(self, bitstream_file):
self.call(["ujprog", bitstream_file])
# EcpDapProgrammer -------------------------------------------------------------------------------
# EcpDapProgrammer ---------------------------------------------------------------------------------
class EcpDapProgrammer(GenericProgrammer):
"""ECPDAP allows you to program ECP5 FPGAs and attached SPI flash using CMSIS-DAP probes in JTAG mode.

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@ -4,19 +4,25 @@
# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
# SPDX-License-Identifier: BSD-2-Clause
#from litex.build import *
from litex.build import tools
# NextPNR Wrapper ----------------------------------------------------------------------------------
class NextPNRWrapper():
"""
NextPNRWrapper NexPNR wrapper
"""
def __init__(self, family="", architecture="", package="", build_name="",
in_format="", out_format="", constr_format="",
pnr_opts="", **kwargs):
def __init__(self,
family = "",
architecture = "",
package = "",
build_name = "",
in_format = "",
out_format = "",
constr_format = "",
pnr_opts = "",
**kwargs) :
"""
Parameters
==========
@ -39,15 +45,15 @@ class NextPNRWrapper():
kwargs: dict
alternate options key/value
"""
self.name = f"nextpnr-{family}"
self._target = family
self._build_name = build_name
self._in_format = in_format
self._out_format = out_format
self.name = f"nextpnr-{family}"
self._target = family
self._build_name = build_name
self._in_format = in_format
self._out_format = out_format
self._constr_format = constr_format
self._pnr_opts = pnr_opts + " "
self._pnr_opts += f"--{architecture} " if architecture != "" else ""
self._pnr_opts += f"--package {package} " if package != "" else ""
self._pnr_opts = pnr_opts + " "
self._pnr_opts += f"--{architecture} " if architecture != "" else ""
self._pnr_opts += f"--package {package} " if package != "" else ""
for key,value in kwargs.items():
key = key.replace("_","-")
if isinstance(value, bool):
@ -72,13 +78,14 @@ class NextPNRWrapper():
" {build_name}.{constr_fmt}" + \
" --{out_fmt} {build_name}.{out_ext} {pnr_opts}\n"
base_cmd = cmd.format(
pnr_name=self.name,
build_name=self._build_name,
in_fmt=self._in_format,
out_fmt="textcfg" if self._out_format == "config" else self._out_format,
out_ext=self._out_format,
constr_fmt=self._constr_format,
pnr_opts=self._pnr_opts)
pnr_name = self.name,
build_name = self._build_name,
in_fmt = self._in_format,
out_fmt = "textcfg" if self._out_format == "config" else self._out_format,
out_ext = self._out_format,
constr_fmt = self._constr_format,
pnr_opts = self._pnr_opts
)
if target == "makefile":
return f"{self._build_name}.{self._out_format}:\n\t" + base_cmd
elif target == "script":

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@ -7,7 +7,7 @@
from litex.build.tools import write_to_file
from litex.build.generic_programmer import GenericProgrammer
# openFPGAloader ------------------------------------------------------------------------------------------
# OpenFPGALoader -----------------------------------------------------------------------------------
class OpenFPGALoader(GenericProgrammer):
needs_bitreverse = False

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@ -9,6 +9,7 @@
from litex.build.tools import write_to_file
from litex.build.generic_programmer import GenericProgrammer
# OpenOCD ------------------------------------------------------------------------------------------
class OpenOCD(GenericProgrammer):
needs_bitreverse = False

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@ -9,6 +9,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.io import *
# OS-FPGA Special Overrides --------------------------------------------------------------------------
# OS-FPGA Special Overrides ------------------------------------------------------------------------
osfpga_special_overrides = {}

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@ -16,7 +16,7 @@ from litex.build.generic_toolchain import GenericToolchain
from litex.build.generic_platform import *
from litex.build import tools
# OSFPGAToolchain -----------------------------------------------------------------------------------
# OSFPGAToolchain ----------------------------------------------------------------------------------
class OSFPGAToolchain(GenericToolchain):
attr_translate = {}

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@ -18,8 +18,8 @@ from litex.build import tools
from litex.build.quicklogic import common
# F4PGAToolchain -------------------------------------------------------------------------------
# Formerly SymbiflowToolchain, Symbiflow has been renamed to F4PGA -----------------------------
# F4PGAToolchain -----------------------------------------------------------------------------------
# Formerly SymbiflowToolchain, Symbiflow has been renamed to F4PGA ---------------------------------
class F4PGAToolchain(GenericToolchain):
attr_translate = {}

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@ -445,8 +445,11 @@ def _build_yosys_project(platform, synth_opts="", build_name=""):
]
yosys = YosysWrapper(platform, build_name,
target="xilinx",
template=[], yosys_cmds=yosys_cmd,
yosys_opts=f"-family {family}", synth_format="edif")
target = "xilinx",
template = [],
yosys_cmds = yosys_cmd,
yosys_opts = f"-family {family}",
synth_format = "edif"
)
yosys.build_script()
return yosys.get_yosys_call("script")

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@ -26,8 +26,8 @@ except ModuleNotFoundError as e:
F4CACHEPATH = '.f4cache'
# F4PGAToolchain -------------------------------------------------------------------------------
# Formerly SymbiflowToolchain, Symbiflow has been renamed to F4PGA -----------------------------
# F4PGAToolchain -----------------------------------------------------------------------------------
# Formerly SymbiflowToolchain, Symbiflow has been renamed to F4PGA ---------------------------------
class F4PGAToolchain(GenericToolchain):
attr_translate = {

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@ -22,7 +22,7 @@ from litex.build.generic_platform import *
from litex.build import tools
from litex.build.xilinx import common
# XilinxISEToolchain --------------------------------------------------------------------------------
# XilinxISEToolchain -------------------------------------------------------------------------------
class XilinxISEToolchain(GenericToolchain):
attr_translate = {
@ -37,14 +37,14 @@ class XilinxISEToolchain(GenericToolchain):
def __init__(self):
super().__init__()
self.xst_opt = "-ifmt MIXED\n-use_new_parser yes\n-opt_mode SPEED\n-register_balancing yes"
self.map_opt = "-ol high -w"
self.par_opt = "-ol high -w"
self.xst_opt = "-ifmt MIXED\n-use_new_parser yes\n-opt_mode SPEED\n-register_balancing yes"
self.map_opt = "-ol high -w"
self.par_opt = "-ol high -w"
self.ngdbuild_opt = ""
self.bitgen_opt = "-g Binary:Yes -w"
self.ise_commands = ""
self._mode = "xst"
self._isemode = "xst"
self._mode = "xst"
self._isemode = "xst"
def build(self, platform, fragment,
mode = "xst",
@ -56,7 +56,7 @@ class XilinxISEToolchain(GenericToolchain):
return GenericToolchain.build(self, platform, fragment, **kwargs)
# Constraints (.ucf) -------------------------------------------------------------------------------
# Constraints (.ucf) ---------------------------------------------------------------------------
@classmethod
def _format_constraint(cls, c):
@ -118,7 +118,7 @@ class XilinxISEToolchain(GenericToolchain):
tools.write_to_file(self._build_name + ".xst", xst_contents)
# ISE Run ------------------------------------------------------------------------------------------
# ISE Run --------------------------------------------------------------------------------------
def build_script(self):
if sys.platform == "win32" or sys.platform == "cygwin":
@ -176,7 +176,6 @@ bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit{fail_stmt}
return build_script_file
def run_script(self, script):
if self._mode == "edif":
# Generate edif
e_output = self.platform.get_edif(self._fragment)

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@ -206,7 +206,7 @@ class Adept(GenericProgrammer):
"prog", "-d", self.board,
"-i", str(self.index),
"-f", bitstream_file,
])
])
def flash(self, address, data_file):
raise ValueError("Flashing unsupported with DigilentAdept tools")

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@ -28,18 +28,10 @@ def _unwrap(value):
return value.value if isinstance(value, Constant) else value
# YosysNextpnrToolchain -------------------------------------------------------------------------------
# YosysNextpnrToolchain ----------------------------------------------------------------------------
class XilinxYosysNextpnrToolchain(YosysNextPNRToolchain):
attr_translate = {
#"keep": ("dont_touch", "true"),
#"no_retiming": ("dont_touch", "true"),
#"async_reg": ("async_reg", "true"),
#"mr_ff": ("mr_ff", "true"), # user-defined attribute
#"ars_ff1": ("ars_ff1", "true"), # user-defined attribute
#"ars_ff2": ("ars_ff2", "true"), # user-defined attribute
#"no_shreg_extract": None
}
attr_translate = {}
family = "xilinx"
synth_fmt = "json"

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@ -1,12 +1,11 @@
#
# This file is part of LiteX.
#
# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
# Copyright (c) 2017-2018 William D. Jones <thor0505@comcast.net>
# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
# SPDX-License-Identifier: BSD-2-Clause
import sys
import subprocess
from shutil import which
@ -16,7 +15,7 @@ from litex.build.generic_toolchain import GenericToolchain
from litex.build.nextpnr_wrapper import NextPNRWrapper
from litex.build.yosys_wrapper import YosysWrapper
# YosysNextPNRToolchain -------------------------------------------------------------------------
# YosysNextPNRToolchain ----------------------------------------------------------------------------
class YosysNextPNRToolchain(GenericToolchain):
"""
@ -166,13 +165,13 @@ class YosysNextPNRToolchain(GenericToolchain):
"""
if sys.platform in ("win32", "cygwin"):
script_ext = ".bat"
script_ext = ".bat"
script_contents = "@echo off\nrem Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n\n"
fail_stmt = " || exit /b"
fail_stmt = " || exit /b"
else:
script_ext = ".sh"
script_ext = ".sh"
script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\nset -e\n"
fail_stmt = ""
fail_stmt = ""
# yosys call
script_contents += self._yosys.get_yosys_call("script") + fail_stmt

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@ -4,20 +4,23 @@
# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build import tools
# YosysWrapper -------------------------------------------------------------------------------------
class YosysWrapper():
"""
YosysWrapper synthesis wrapper
"""
def __init__(self, platform, build_name, target="", output_name="",
template=[], yosys_opts="",
yosys_cmds=[],
synth_format="json",
**kwargs):
def __init__(self, platform, build_name,
target = "",
output_name = "",
template = [],
yosys_opts = "",
yosys_cmds = [],
synth_format = "json",
**kwargs) :
"""
Parameters
==========
@ -41,21 +44,21 @@ class YosysWrapper():
list of key/value for yosys_opts [optional]
"""
assert platform != ""
assert build_name != ""
assert target != ""
assert platform != ""
assert build_name != ""
assert target != ""
assert synth_format != ""
self._template = self._default_template if template == [] else template
self._template = self._default_template if template == [] else template
self._output_name = build_name if output_name == "" else output_name
self._platform = platform
self._build_name = build_name
self._platform = platform
self._build_name = build_name
self._synth_format = synth_format
self._yosys_opts = yosys_opts
self._yosys_cmds = yosys_cmds
self._yosys_opts = yosys_opts
self._yosys_cmds = yosys_cmds
self._target=target
self._target = target
for key,value in kwargs.items():
key = key.replace("_","-")