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cores/cpu/femtorv: Add initial variants support (With Quark and Tachyon for now).

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This commit is contained in:
Florent Kermarrec 2021-11-19 16:31:20 +01:00
parent 54a4e6c1f6
commit 3c3884b1ea
1 changed files with 27 additions and 6 deletions
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33
litex/soc/cores/cpu/femtorv/core.py
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@ -13,7 +13,26 @@ from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# Variants -----------------------------------------------------------------------------------------
CPU_VARIANTS = ["standard"]
CPU_VARIANTS = {
"standard": "femtorv32_quark",
"quark": "femtorv32_quark", # The most elementary version of FemtoRV32.
"tachyon": "femtorv32_tachyon", # Quark with the EXECUTE is splitted into two steps, higher freq.
}
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"standard": "-march=rv32 -mabi=ilp32",
"quark": "-march=rv32i -mabi=ilp32",
"tachyon": "-march=rv32i -mabi=ilp32",
}
# FemtoRV ------------------------------------------------------------------------------------------
@ -40,6 +59,7 @@ class FemtoRV(CPU):
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.human_name = f"FemtoRV-{variant.upper()}"
self.reset = Signal()
self.idbus = idbus = wishbone.Interface()
self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
@ -134,7 +154,7 @@ class FemtoRV(CPU):
# Add Verilog sources.
# --------------------
self.add_sources(platform)
self.add_sources(platform, variant)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
@ -142,11 +162,12 @@ class FemtoRV(CPU):
self.cpu_params.update(p_RESET_ADDR=Constant(reset_address, 32))
@staticmethod
def add_sources(platform):
if not os.path.exists("femtorv32_quark.v"):
def add_sources(platform, variant):
cpu_filename = f"femtorv32_{variant}.v"
if not os.path.exists(cpu_filename):
# Get FemtoRV32 source.
os.system("wget https://raw.githubusercontent.com/BrunoLevy/learn-fpga/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v")
platform.add_source("femtorv32_quark.v")
os.system(f"wget https://raw.githubusercontent.com/BrunoLevy/learn-fpga/master/FemtoRV/RTL/PROCESSOR/{cpu_filename}")
platform.add_source(cpu_filename)
def do_finalize(self):
assert hasattr(self, "reset_address")