soc/interconnect/dma_lasmi: change endpoint names

This commit is contained in:
Florent Kermarrec 2016-04-13 18:28:52 +02:00
parent 6e0045e6be
commit 3d222d9e63
1 changed files with 18 additions and 17 deletions

View File

@ -5,8 +5,8 @@ from litex.soc.interconnect import stream
class Reader(Module): class Reader(Module):
def __init__(self, lasmim, fifo_depth=None): def __init__(self, lasmim, fifo_depth=None):
self.address = stream.Endpoint([("a", lasmim.aw)]) self.sink = sink = stream.Endpoint([("address", lasmim.aw)])
self.data = stream.Endpoint([("d", lasmim.dw)]) self.source = source = stream.Endpoint([("data", lasmim.dw)])
self.busy = Signal() self.busy = Signal()
# # # # # #
@ -20,9 +20,9 @@ class Reader(Module):
self.comb += [ self.comb += [
lasmim.we.eq(0), lasmim.we.eq(0),
lasmim.stb.eq(self.address.valid & request_enable), lasmim.stb.eq(sink.valid & request_enable),
lasmim.adr.eq(self.address.a), lasmim.adr.eq(sink.address),
self.address.ready.eq(lasmim.req_ack & request_enable), sink.ready.eq(lasmim.req_ack & request_enable),
request_issued.eq(lasmim.stb & lasmim.req_ack) request_issued.eq(lasmim.stb & lasmim.req_ack)
] ]
@ -51,16 +51,17 @@ class Reader(Module):
fifo.din.eq(lasmim.dat_r), fifo.din.eq(lasmim.dat_r),
fifo.we.eq(lasmim.dat_r_ack), fifo.we.eq(lasmim.dat_r_ack),
self.data.valid.eq(fifo.readable), source.valid.eq(fifo.readable),
fifo.re.eq(self.data.ready), fifo.re.eq(source.ready),
self.data.d.eq(fifo.dout), source.data.eq(fifo.dout),
data_dequeued.eq(self.data.valid & self.data.ready) data_dequeued.eq(source.valid & source.ready)
] ]
class Writer(Module): class Writer(Module):
def __init__(self, lasmim, fifo_depth=None): def __init__(self, lasmim, fifo_depth=None):
self.address_data = stream.Endpoint([("a", lasmim.aw), ("d", lasmim.dw)]) self.source = source = stream.Endpoint([("address", lasmim.aw),
("data", lasmim.dw)])
self.busy = Signal() self.busy = Signal()
# # # # # #
@ -73,11 +74,11 @@ class Writer(Module):
self.comb += [ self.comb += [
lasmim.we.eq(1), lasmim.we.eq(1),
lasmim.stb.eq(fifo.writable & self.address_data.valid), lasmim.stb.eq(fifo.writable & source.valid),
lasmim.adr.eq(self.address_data.a), lasmim.adr.eq(source.address),
self.address_data.ready.eq(fifo.writable & lasmim.req_ack), source.ready.eq(fifo.writable & lasmim.req_ack),
fifo.we.eq(self.address_data.valid & lasmim.req_ack), fifo.we.eq(source.valid & lasmim.req_ack),
fifo.din.eq(self.address_data.d) fifo.din.eq(source.data)
] ]
self.comb += [ self.comb += [