soc/interconnect/dma_lasmi: change endpoint names
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6e0045e6be
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3d222d9e63
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@ -5,8 +5,8 @@ from litex.soc.interconnect import stream
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class Reader(Module):
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class Reader(Module):
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def __init__(self, lasmim, fifo_depth=None):
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def __init__(self, lasmim, fifo_depth=None):
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self.address = stream.Endpoint([("a", lasmim.aw)])
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self.sink = sink = stream.Endpoint([("address", lasmim.aw)])
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self.data = stream.Endpoint([("d", lasmim.dw)])
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self.source = source = stream.Endpoint([("data", lasmim.dw)])
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self.busy = Signal()
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self.busy = Signal()
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# # #
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# # #
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@ -20,9 +20,9 @@ class Reader(Module):
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self.comb += [
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self.comb += [
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lasmim.we.eq(0),
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lasmim.we.eq(0),
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lasmim.stb.eq(self.address.valid & request_enable),
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lasmim.stb.eq(sink.valid & request_enable),
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lasmim.adr.eq(self.address.a),
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lasmim.adr.eq(sink.address),
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self.address.ready.eq(lasmim.req_ack & request_enable),
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sink.ready.eq(lasmim.req_ack & request_enable),
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request_issued.eq(lasmim.stb & lasmim.req_ack)
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request_issued.eq(lasmim.stb & lasmim.req_ack)
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]
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]
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@ -51,16 +51,17 @@ class Reader(Module):
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fifo.din.eq(lasmim.dat_r),
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fifo.din.eq(lasmim.dat_r),
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fifo.we.eq(lasmim.dat_r_ack),
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fifo.we.eq(lasmim.dat_r_ack),
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self.data.valid.eq(fifo.readable),
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source.valid.eq(fifo.readable),
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fifo.re.eq(self.data.ready),
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fifo.re.eq(source.ready),
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self.data.d.eq(fifo.dout),
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source.data.eq(fifo.dout),
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data_dequeued.eq(self.data.valid & self.data.ready)
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data_dequeued.eq(source.valid & source.ready)
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]
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]
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class Writer(Module):
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class Writer(Module):
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def __init__(self, lasmim, fifo_depth=None):
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def __init__(self, lasmim, fifo_depth=None):
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self.address_data = stream.Endpoint([("a", lasmim.aw), ("d", lasmim.dw)])
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self.source = source = stream.Endpoint([("address", lasmim.aw),
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("data", lasmim.dw)])
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self.busy = Signal()
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self.busy = Signal()
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# # #
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# # #
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@ -73,11 +74,11 @@ class Writer(Module):
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self.comb += [
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self.comb += [
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lasmim.we.eq(1),
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lasmim.we.eq(1),
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lasmim.stb.eq(fifo.writable & self.address_data.valid),
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lasmim.stb.eq(fifo.writable & source.valid),
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lasmim.adr.eq(self.address_data.a),
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lasmim.adr.eq(source.address),
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self.address_data.ready.eq(fifo.writable & lasmim.req_ack),
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source.ready.eq(fifo.writable & lasmim.req_ack),
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fifo.we.eq(self.address_data.valid & lasmim.req_ack),
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fifo.we.eq(source.valid & lasmim.req_ack),
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fifo.din.eq(self.address_data.d)
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fifo.din.eq(source.data)
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]
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]
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self.comb += [
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self.comb += [
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