software/liblitedram: add initial write latency calibration.
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3518223c84
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3d5bc29dd1
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@ -519,24 +519,6 @@ int sdram_write_leveling(void)
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int cdly_range_start;
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int cdly_range_start;
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int cdly_range_end;
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int cdly_range_end;
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int cdly_range_step;
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int cdly_range_step;
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int i, j;
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/* Configure write bitslips */
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for (i=0; i<16; i++) {
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/* sel module */
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ddrphy_dly_sel_write(1 << i);
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/* rst bitslip */
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ddrphy_wdly_dq_bitslip_rst_write(1);
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/* set bitslip */
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if (_sdram_write_leveling_bitslips[i] >= 0) {
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for (j=0; j<_sdram_write_leveling_bitslips[i]; j++) {
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ddrphy_wdly_dq_bitslip_write(1);
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}
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}
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/* unsel module */
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ddrphy_dly_sel_write(0);
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}
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if (_sdram_write_leveling_cmd_scan) {
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if (_sdram_write_leveling_cmd_scan) {
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printf(" Cmd/Clk scan:\n");
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printf(" Cmd/Clk scan:\n");
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@ -721,7 +703,7 @@ static int sdram_write_read_check_test_pattern(int module, unsigned int seed) {
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return 1;
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return 1;
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}
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}
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static int sdram_read_leveling_scan_module(int module, int bitslip)
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static int sdram_read_leveling_scan_module(int module, int bitslip, int show)
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{
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{
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int i;
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int i;
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int score;
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int score;
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@ -731,22 +713,24 @@ static int sdram_read_leveling_scan_module(int module, int bitslip)
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/* Check test pattern for each delay value */
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/* Check test pattern for each delay value */
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score = 0;
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score = 0;
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printf(" m%d, b%d: |", module, bitslip);
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if (show)
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printf(" m%d, b%d: |", module, bitslip);
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sdram_read_leveling_rst_delay(module);
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sdram_read_leveling_rst_delay(module);
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for(i=0;i<SDRAM_PHY_DELAYS;i++) {
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for(i=0;i<SDRAM_PHY_DELAYS;i++) {
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int working;
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int working;
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int show = 1;
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int _show = show;
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#if SDRAM_PHY_DELAYS > 32
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#if SDRAM_PHY_DELAYS > 32
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show = (i%16 == 0);
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_show = (i%16 == 0) & show;
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#endif
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#endif
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working = sdram_write_read_check_test_pattern(module, 42);
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working = sdram_write_read_check_test_pattern(module, 42);
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working &= sdram_write_read_check_test_pattern(module, 43);
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working &= sdram_write_read_check_test_pattern(module, 43);
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if (show)
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if (_show)
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printf("%d", working);
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printf("%d", working);
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score += working;
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score += working;
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sdram_read_leveling_inc_delay(module);
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sdram_read_leveling_inc_delay(module);
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}
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}
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printf("| ");
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if (show)
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printf("| ");
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/* Precharge */
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/* Precharge */
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sdram_precharge_test_row();
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sdram_precharge_test_row();
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@ -839,7 +823,7 @@ void sdram_read_leveling(void)
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best_bitslip = 0;
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best_bitslip = 0;
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for(bitslip=0; bitslip<SDRAM_PHY_BITSLIPS; bitslip++) {
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for(bitslip=0; bitslip<SDRAM_PHY_BITSLIPS; bitslip++) {
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/* Compute score */
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/* Compute score */
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score = sdram_read_leveling_scan_module(module, bitslip);
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score = sdram_read_leveling_scan_module(module, bitslip, 1);
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sdram_read_leveling_module(module);
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sdram_read_leveling_module(module);
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printf("\n");
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printf("\n");
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if (score > best_score) {
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if (score > best_score) {
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@ -865,6 +849,66 @@ void sdram_read_leveling(void)
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}
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}
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}
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}
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/*-----------------------------------------------------------------------*/
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/* Write latency calibration */
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/*-----------------------------------------------------------------------*/
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static void sdram_write_latency_calibration(void) {
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int i;
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int module;
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int bitslip;
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int score;
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int best_score;
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int best_bitslip;
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for(module=0; module<SDRAM_PHY_MODULES; module++) {
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/* Scan possible write windows */
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best_score = 0;
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best_bitslip = 0;
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for(bitslip=0; bitslip<SDRAM_PHY_BITSLIPS; bitslip++) {
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score = 0;
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/* sel module */
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ddrphy_dly_sel_write(1 << module);
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/* rst bitslip */
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ddrphy_wdly_dq_bitslip_rst_write(1);
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for (i=0; i<bitslip; i++) {
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ddrphy_wdly_dq_bitslip_write(1);
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}
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/* unsel module */
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ddrphy_dly_sel_write(0);
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score = 0;
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sdram_read_leveling_rst_bitslip(module);
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for(i=0; i<SDRAM_PHY_BITSLIPS; i++) {
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/* Compute score */
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score += sdram_read_leveling_scan_module(module, i, 0);
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/* Increment bitslip */
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sdram_read_leveling_inc_bitslip(module);
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}
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if (score > best_score) {
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best_bitslip = bitslip;
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best_score = score;
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}
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}
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if (_sdram_write_leveling_bitslips[module] < 0)
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bitslip = best_bitslip;
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else
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bitslip = _sdram_write_leveling_bitslips[module];
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printf("m%d:%d ", module, bitslip);
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/* Select best write window */
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ddrphy_dly_sel_write(1 << module);
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/* rst bitslip */
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ddrphy_wdly_dq_bitslip_rst_write(1);
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for (i=0; i<bitslip; i++) {
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ddrphy_wdly_dq_bitslip_write(1);
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}
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/* unsel module */
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ddrphy_dly_sel_write(0);
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}
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printf("\n");
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}
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/*-----------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------*/
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/* Leveling */
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/* Leveling */
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/*-----------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------*/
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@ -887,6 +931,9 @@ int sdram_leveling(void)
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sdram_write_leveling();
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sdram_write_leveling();
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#endif
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#endif
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printf("Write latency calibration:\n");
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sdram_write_latency_calibration();
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#ifdef SDRAM_PHY_READ_LEVELING_CAPABLE
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#ifdef SDRAM_PHY_READ_LEVELING_CAPABLE
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printf("Read leveling:\n");
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printf("Read leveling:\n");
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sdram_read_leveling();
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sdram_read_leveling();
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