Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/soc: Be sure all add_xy methods use check_if_exists, improve Video integration.

This commit is contained in:
Florent Kermarrec 2021-03-25 09:29:33 +01:00
parent c9ac5424f4
commit 3def6ae985
1 changed files with 32 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
litex/soc/integration/soc.py
View File

@ -833,6 +833,7 @@ class SoC(Module):
"wishbone": wishbone.Wishbone2CSR, "wishbone": wishbone.Wishbone2CSR,
"axi-lite": axi.AXILite2CSR, "axi-lite": axi.AXILite2CSR,
}[self.bus.standard] }[self.bus.standard]
self.check_if_exists("csr_bridge")
self.submodules.csr_bridge = csr_bridge_cls( self.submodules.csr_bridge = csr_bridge_cls(
bus_csr = csr_bus.Interface( bus_csr = csr_bus.Interface(
address_width = self.csr.address_width, address_width = self.csr.address_width,
@ -868,6 +869,7 @@ class SoC(Module):
colorer("not supported", color="red"), colorer("not supported", color="red"),
colorer(", ".join(cpu_cls.variants)))) colorer(", ".join(cpu_cls.variants))))
raise raise
self.check_if_exists("cpu")
self.submodules.cpu = cpu_cls(self.platform, variant) self.submodules.cpu = cpu_cls(self.platform, variant)
# Update SoC with CPU constraints. # Update SoC with CPU constraints.
@ -1102,6 +1104,7 @@ class LiteXSoC(SoC):
# Add UART ------------------------------------------------------------------------------------- # Add UART -------------------------------------------------------------------------------------
def add_uart(self, name, baudrate=115200, fifo_depth=16): def add_uart(self, name, baudrate=115200, fifo_depth=16):
from litex.soc.cores import uart from litex.soc.cores import uart
self.check_if_exists("uart")
# Stub / Stream. # Stub / Stream.
if name in ["stub", "stream"]: if name in ["stub", "stream"]:
@ -1183,6 +1186,7 @@ class LiteXSoC(SoC):
from litex.soc.cores import uart from litex.soc.cores import uart
if clk_freq is None: if clk_freq is None:
clk_freq = self.sys_clk_freq clk_freq = self.sys_clk_freq
self.check_if_exists("uartbone")
self.submodules.uartbone_phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate) self.submodules.uartbone_phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate)
self.csr.add("uartbone_phy") self.csr.add("uartbone_phy")
self.submodules.uartbone = uart.UARTBone(phy=self.uartbone_phy, clk_freq=clk_freq, cd=cd) self.submodules.uartbone = uart.UARTBone(phy=self.uartbone_phy, clk_freq=clk_freq, cd=cd)
@ -1192,6 +1196,7 @@ class LiteXSoC(SoC):
def add_jtagbone(self): def add_jtagbone(self):
from litex.soc.cores import uart from litex.soc.cores import uart
from litex.soc.cores.jtag import JTAGPHY from litex.soc.cores.jtag import JTAGPHY
self.check_if_exists("jtabone")
self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device) self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device)
self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq) self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq)
self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone) self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)
@ -1212,6 +1217,7 @@ class LiteXSoC(SoC):
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
# LiteDRAM core. # LiteDRAM core.
self.check_if_exists("sdram")
self.submodules.sdram = LiteDRAMCore( self.submodules.sdram = LiteDRAMCore(
phy = phy, phy = phy,
geom_settings = module.geom_settings, geom_settings = module.geom_settings,
@ -1365,6 +1371,7 @@ class LiteXSoC(SoC):
from liteeth.phy.model import LiteEthPHYModel from liteeth.phy.model import LiteEthPHYModel
# MAC. # MAC.
self.check_if_exists(name)
ethmac = LiteEthMAC( ethmac = LiteEthMAC(
phy = phy, phy = phy,
dw = 32, dw = 32,
@ -1416,6 +1423,7 @@ class LiteXSoC(SoC):
from liteeth.phy.model import LiteEthPHYModel from liteeth.phy.model import LiteEthPHYModel
# Core # Core
self.check_if_exists(name)
ethcore = LiteEthUDPIPCore( ethcore = LiteEthUDPIPCore(
phy = phy, phy = phy,
mac_address = mac_address, mac_address = mac_address,
@ -1457,6 +1465,7 @@ class LiteXSoC(SoC):
if clk_freq is None: clk_freq = self.clk_freq/2 # FIXME: Get max clk_freq from SPI Flash if clk_freq is None: clk_freq = self.clk_freq/2 # FIXME: Get max clk_freq from SPI Flash
# Core. # Core.
self.check_if_exists(name)
spiflash = SpiFlash( spiflash = SpiFlash(
pads = self.platform.request(name if mode == "1x" else name + mode), pads = self.platform.request(name if mode == "1x" else name + mode),
dummy = dummy_cycles, dummy = dummy_cycles,
@ -1480,6 +1489,7 @@ class LiteXSoC(SoC):
self.comb += pads.rst.eq(0) self.comb += pads.rst.eq(0)
# Core. # Core.
self.check_if_exists(name)
spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq) spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq)
spisdcard.add_clk_divider() spisdcard.add_clk_divider()
setattr(self.submodules, name, spisdcard) setattr(self.submodules, name, spisdcard)
@ -1509,6 +1519,8 @@ class LiteXSoC(SoC):
sdcard_pads = self.platform.request(name) sdcard_pads = self.platform.request(name)
# Core. # Core.
self.check_if_exists("sdphy")
self.check_if_exists("sdcore")
self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq, cmd_timeout=10e-1, data_timeout=10e-1) self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq, cmd_timeout=10e-1, data_timeout=10e-1)
self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdcore = SDCore(self.sdphy)
self.csr.add("sdphy", use_loc_if_exists=True) self.csr.add("sdphy", use_loc_if_exists=True)
@ -1567,9 +1579,11 @@ class LiteXSoC(SoC):
assert self.clk_freq >= sata_clk_freq/2 # FIXME: /2 for 16-bit data-width, add support for 32-bit. assert self.clk_freq >= sata_clk_freq/2 # FIXME: /2 for 16-bit data-width, add support for 32-bit.
# Core. # Core.
self.check_if_exists("sata_core")
self.submodules.sata_core = LiteSATACore(phy) self.submodules.sata_core = LiteSATACore(phy)
# Crossbar. # Crossbar.
self.check_if_exists("sata_crossbar")
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core) self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# Sector2Mem DMA. # Sector2Mem DMA.
@ -1614,16 +1628,19 @@ class LiteXSoC(SoC):
assert not hasattr(self, f"{name}_endpoint") assert not hasattr(self, f"{name}_endpoint")
# Endpoint. # Endpoint.
self.check_if_exists(f"{name}_endpoint")
endpoint = LitePCIeEndpoint(phy, max_pending_requests=max_pending_requests) endpoint = LitePCIeEndpoint(phy, max_pending_requests=max_pending_requests)
setattr(self.submodules, f"{name}_endpoint", endpoint) setattr(self.submodules, f"{name}_endpoint", endpoint)
# MMAP. # MMAP.
self.check_if_exists(f"{name}_mmap")
mmap = LitePCIeWishboneMaster(self.pcie_endpoint, base_address=self.mem_map["csr"]) mmap = LitePCIeWishboneMaster(self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(mmap.wishbone) self.add_wb_master(mmap.wishbone)
setattr(self.submodules, f"{name}_mmap", mmap) setattr(self.submodules, f"{name}_mmap", mmap)
# MSI. # MSI.
if with_msi: if with_msi:
self.check_if_exists(f"{name}_msi")
msi = LitePCIeMSI() msi = LitePCIeMSI()
setattr(self.submodules, f"{name}_msi", msi) setattr(self.submodules, f"{name}_msi", msi)
self.csr.add(f"{name}_msi") self.csr.add(f"{name}_msi")
@ -1633,6 +1650,7 @@ class LiteXSoC(SoC):
# DMAs. # DMAs.
for i in range(ndmas): for i in range(ndmas):
assert with_msi assert with_msi
self.check_if_exists(f"{name}_dma{i}")
dma = LitePCIeDMA(phy, endpoint, dma = LitePCIeDMA(phy, endpoint,
with_buffering = True, buffering_depth=1024, with_buffering = True, buffering_depth=1024,
with_loopback = True) with_loopback = True)
@ -1657,14 +1675,16 @@ class LiteXSoC(SoC):
from litex.soc.cores.video import VideoTimingGenerator, ColorBarsPattern from litex.soc.cores.video import VideoTimingGenerator, ColorBarsPattern
# Video Timing Generator. # Video Timing Generator.
self.check_if_exists(f"{name}_vtg")
vtg = VideoTimingGenerator(default_video_timings=timings) vtg = VideoTimingGenerator(default_video_timings=timings)
vtg = ClockDomainsRenamer(clock_domain)(vtg) vtg = ClockDomainsRenamer(clock_domain)(vtg)
self.submodules.video_colorbars_vtg = vtg setattr(self.submodules, f"{name}_vtg", vtg)
self.csr.add("video_colorbars_vtg") self.csr.add(f"{name}_vtg")
# ColorsBars Pattern. # ColorsBars Pattern.
self.check_if_exists(name)
colorbars = ClockDomainsRenamer(clock_domain)(ColorBarsPattern()) colorbars = ClockDomainsRenamer(clock_domain)(ColorBarsPattern())
self.submodules.video_colorbars = colorbars setattr(self.submodules, name, colorbars)
# Connect Video Timing Generator to ColorsBars Pattern. # Connect Video Timing Generator to ColorsBars Pattern.
self.comb += [ self.comb += [
@ -1678,10 +1698,11 @@ class LiteXSoC(SoC):
from litex.soc.cores.video import VideoTimingGenerator, VideoTerminal from litex.soc.cores.video import VideoTimingGenerator, VideoTerminal
# Video Timing Generator. # Video Timing Generator.
self.check_if_exists(f"{name}_vtg")
vtg = VideoTimingGenerator(default_video_timings=timings) vtg = VideoTimingGenerator(default_video_timings=timings)
vtg = ClockDomainsRenamer(clock_domain)(vtg) vtg = ClockDomainsRenamer(clock_domain)(vtg)
self.submodules.video_terminal_vtg = vtg setattr(self.submodules, f"{name}_vtg", vtg)
self.csr.add("video_terminal_vtg") self.csr.add(f"{name}_vtg")
# Video Terminal. # Video Terminal.
vt = VideoTerminal( vt = VideoTerminal(
@ -1689,14 +1710,14 @@ class LiteXSoC(SoC):
vres = int(timings.split("@")[0].split("x")[1]), vres = int(timings.split("@")[0].split("x")[1]),
) )
vt = ClockDomainsRenamer(clock_domain)(vt) vt = ClockDomainsRenamer(clock_domain)(vt)
self.submodules.video_terminal = vt setattr(self.submodules, name, vt)
# Connect Video Timing Generator to Video Terminal. # Connect Video Timing Generator to Video Terminal.
self.comb += vtg.source.connect(vt.vtg_sink) self.comb += vtg.source.connect(vt.vtg_sink)
# Connect UART to Video Terminal. # Connect UART to Video Terminal.
uart_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=clock_domain) uart_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=clock_domain)
self.submodules.video_terminal_uart_cdc = uart_cdc setattr(self.submodules, f"{name}_uart_cdc", uart_cdc)
self.comb += [ self.comb += [
uart_cdc.sink.valid.eq(self.uart.source.valid & self.uart.source.ready), uart_cdc.sink.valid.eq(self.uart.source.valid & self.uart.source.ready),
uart_cdc.sink.data.eq(self.uart.source.data), uart_cdc.sink.data.eq(self.uart.source.data),
@ -1714,8 +1735,8 @@ class LiteXSoC(SoC):
# Video Timing Generator. # Video Timing Generator.
vtg = VideoTimingGenerator(default_video_timings=timings) vtg = VideoTimingGenerator(default_video_timings=timings)
vtg = ClockDomainsRenamer(clock_domain)(vtg) vtg = ClockDomainsRenamer(clock_domain)(vtg)
self.submodules.video_framebuffer_vtg = vtg setattr(self.submodules, f"{name}_vtg", vtg)
self.csr.add("video_framebuffer_vtg") self.csr.add(f"{name}_vtg")
# Video FrameBuffer. # Video FrameBuffer.
vfb = VideoFrameBuffer(self.sdram.crossbar.get_port(), vfb = VideoFrameBuffer(self.sdram.crossbar.get_port(),
@ -1723,8 +1744,8 @@ class LiteXSoC(SoC):
vres = int(timings.split("@")[0].split("x")[1]), vres = int(timings.split("@")[0].split("x")[1]),
clock_domain = clock_domain clock_domain = clock_domain
) )
self.submodules.video_framebuffer = vfb setattr(self.submodules, name, vfb)
self.csr.add("video_framebuffer") self.csr.add(name)
# Connect Video Timing Generator to Video FrameBuffer. # Connect Video Timing Generator to Video FrameBuffer.
self.comb += vtg.source.connect(vfb.vtg_sink) self.comb += vtg.source.connect(vfb.vtg_sink)