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xilinx/common: be sure language is not vhdl when yosys synthesis is used

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Florent Kermarrec 2019-10-07 10:36:32 +02:00
parent 975bd9be8b
commit 3e22d4b9e6
1 changed files with 1 additions and 0 deletions
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litex/build/xilinx/common.py
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@ -241,6 +241,7 @@ def _run_yosys(device, sources, vincpaths, build_name):
for path in vincpaths: for path in vincpaths:
incflags += " -I" + path incflags += " -I" + path
for filename, language, library in sources: for filename, language, library in sources:
assert language != "vhdl"
ys_contents += "read_{}{} {}\n".format(language, incflags, filename) ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
ys_contents += """\ ys_contents += """\