vivado: permit resources without pins
This is required if the LOC is done by another, external constraints set, as in the case of the Zynq Processing System Instance.
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@ -19,9 +19,11 @@ def _format_constraint(c):
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return "set_property DRIVE " + str(c.strength)
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return "set_property DRIVE " + str(c.strength)
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elif isinstance(c, Misc):
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elif isinstance(c, Misc):
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return "set_property " + c.misc.replace("=", " ")
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return "set_property " + c.misc.replace("=", " ")
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else:
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raise ValueError("unknown constraint %s" % c)
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def _format_xdc(signame, pin, others, resname):
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def _format_xdc(signame, resname, *constraints):
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fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
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fmt_c = [_format_constraint(c) for c in constraints]
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fmt_r = resname[0] + ":" + str(resname[1])
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fmt_r = resname[0] + ":" + str(resname[1])
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if resname[2] is not None:
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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fmt_r += "." + resname[2]
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@ -35,9 +37,11 @@ def _build_xdc(named_sc, named_pc):
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for sig, pins, others, resname in named_sc:
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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for i, p in enumerate(pins):
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r += _format_xdc(sig + "[" + str(i) + "]", p, others, resname)
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r += _format_xdc(sig + "[" + str(i) + "]", resname, Pins(p), *others)
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elif pins:
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r += _format_xdc(sig, resname, Pins(pins[0]), *others)
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else:
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else:
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r += _format_xdc(sig, pins[0], others, resname)
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r += _format_xdc(sig, resname, *others)
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if named_pc:
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if named_pc:
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r += "\n" + "\n\n".join(named_pc)
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r += "\n" + "\n\n".join(named_pc)
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return r
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return r
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