use similar names for wishbone bridges and move wishbone drivers to [core]/software

misoclib/com/liteeth/example_designs/targets/base.py

@@ -4,10 +4,11 @@ from migen.genlib.io import CRG
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
+from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
 from misoclib.com.liteeth.core import LiteEthUDPIPCore
@@ -30,7 +31,7 @@ class BaseSoC(SoC, AutoCSR):
             with_identifier=True,
             with_timer=False
         )
-        self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200))
+        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
         self.add_wb_master(self.cpu_or_bridge.wishbone)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 

misoclib/com/liteeth/example_designs/test/make.py

@@ -19,12 +19,12 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.software.driver.uart import LiteScopeUART2WishboneDriver
+        from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+        wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
-        from misoclib.tools.litescope.software.driver.etherbone import LiteScopeEtherboneDriver
-        wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
+        from misoclib.com.liteeth.software.wishbone import LiteETHWishboneBridgeDriver
+        wb = LiteETHWishboneBridgeDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
     else:
         ValueError("Invalid bridge {}".format(args.bridge))
 

misoclib/com/liteeth/frontend/etherbone/__init__.py

@@ -1,8 +1,8 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.etherbone.packet import *
-from misoclib.com.liteeth.core.etherbone.probe import *
-from misoclib.com.liteeth.core.etherbone.record import *
-from misoclib.com.liteeth.core.etherbone.wishbone import *
+from misoclib.com.liteeth.frontend.etherbone.packet import *
+from misoclib.com.liteeth.frontend.etherbone.probe import *
+from misoclib.com.liteeth.frontend.etherbone.record import *
+from misoclib.com.liteeth.frontend.etherbone.wishbone import *
 
 
 class LiteEthEtherbone(Module):

misoclib/com/liteeth/software/wishbone.py

@@ -1,10 +1,11 @@
 import socket
+
 from misoclib.tools.litescope.software.driver.reg import *
 
 from liteeth.test.model.etherbone import *
 
 
-class LiteScopeEtherboneDriver:
+class LiteEthWishboneDriver:
     def __init__(self, ip_address, udp_port=20000, addrmap=None, busword=8, debug=False):
         self.ip_address = ip_address
         self.udp_port = udp_port

misoclib/com/litepcie/example_designs/targets/dma.py

@@ -6,13 +6,14 @@ from migen.genlib.misc import timeline
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
+
+from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
 
 from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
 from misoclib.com.litepcie.core import Endpoint
 from misoclib.com.litepcie.core.irq.interrupt_controller import InterruptController
 from misoclib.com.litepcie.frontend.dma import DMA
-from misoclib.com.litepcie.frontend.bridge.wishbone import WishboneBridge
+from misoclib.com.litepcie.frontend.wishbone import LitePCIeWishboneBridge
 
 
 class _CRG(Module, AutoCSR):
@@ -74,7 +75,7 @@ class PCIeDMASoC(SoC, AutoCSR):
         self.submodules.pcie_endpoint = Endpoint(self.pcie_phy, with_reordering=True)
 
         # PCIe Wishbone bridge
-        self.add_cpu_or_bridge(WishboneBridge(self.pcie_endpoint, lambda a: 1))
+        self.add_cpu_or_bridge(LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1))
         self.add_wb_master(self.cpu_or_bridge.wishbone)
 
         # PCIe DMA
@@ -82,7 +83,7 @@ class PCIeDMASoC(SoC, AutoCSR):
         self.dma.source.connect(self.dma.sink)
 
         if with_uart_bridge:
-            self.submodules.uart_bridge = LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200)
+            self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
             self.add_wb_master(self.uart_bridge.wishbone)
 
         # IRQs

misoclib/com/litepcie/example_designs/test/make.py

@@ -21,15 +21,15 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.software.driver.uart import LiteScopeUART2WishboneDriver
+        from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+        wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
-        from misoclib.tools.litescope.software.driver.etherbone import LiteScopeEtherboneDriver
-        wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
+        from misoclib.com.liteeth.software.wishbone import LiteETHWishboneDriver
+        wb = LiteETHWishboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "pcie":
-        from misoclib.tools.litescope.software.driver.pcie import LiteScopePCIeDriver
-        wb = LiteScopePCIeDriver(args.bar, args.bar_size, "./csr.csv", int(args.busword), debug=False)
+        from misoclib.com.litepcie.software.linux.wishbone import LitePCIeWishboneDriver
+        wb = LitePCIeWishboneDriver(args.bar, args.bar_size, "./csr.csv", int(args.busword), debug=False)
     else:
         ValueError("Invalid bridge {}".format(args.bridge))
 

misoclib/com/litepcie/frontend/wishbone.py

@@ -5,7 +5,7 @@ from migen.bus import wishbone
 from misoclib.com.litepcie.common import *
 
 
-class WishboneBridge(Module):
+class LitePCIeWishboneBridge(Module):
     def __init__(self, endpoint, address_decoder):
         self.wishbone = wishbone.Interface()
 

misoclib/com/litepcie/software/wishbone.py

@@ -1,9 +1,11 @@
 import string
 import mmap
+import sys
+
 from misoclib.tools.litescope.software.driver.reg import *
 
 
-class LiteScopePCIeDriver:
+class LitePCIeWishboneDriverLinux:
     def __init__(self, bar, bar_size, addrmap=None, busword=8, debug=False):
         self.bar = bar
         self.bar_size = bar_size
@@ -54,3 +56,10 @@ class LiteScopePCIeDriver:
             self.mmap[addr + 4*i:addr + 4*(i+1)] = bytes(dat_bytes)
             if self.debug:
                 print("WR {:08X} @ {:08X}".format(dat, (addr + i)*4))
+
+
+def LitePCIeWishboneDriver(*args, **kwargs):
+    if sys.platform == "win32" or sys.platform == "cygwin":
+        raise NotImplementedError
+    else:
+        return LitePCIeWishboneDriverLinux(*args, **kwargs)

misoclib/com/liteusb/software/wishbone.py

@@ -1,6 +1,6 @@
 from misoclib.com.liteusb.software.ftdi import FTDIComDevice
 
-class LiteScopeUSB2WishboneFTDIDriver:
+class LiteUSBWishboneDriverFTDI:
     cmds = {
         "write": 0x01,
         "read":  0x02
@@ -69,3 +69,10 @@ class LiteScopeUSB2WishboneFTDIDriver:
                 dat = dat << 8
             if self.debug:
                 print("WR {:08X} @ {:08X}".format(data[i], addr + 4*i))
+
+
+def LiteUSBWishboneDriver(chip="ft2232h", *args, **kwargs):
+    drivers = {
+        "ft2232h": LiteUSBWishboneDriverFTDI
+    }
+    return drivers[chip](*args, **kwargs)

misoclib/com/uart/frontend/wishbone.py

@@ -0,0 +1,9 @@
+from migen.fhdl.std import *
+
+from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
+from misoclib.com.uart.phy.serial import UARTPHYSerial
+
+class UARTWishboneBridge(LiteScopeWishboneBridge):
+    def __init__(self, pads, clk_freq, baudrate=115200):
+        self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
+        LiteScopeWishboneBridge.__init__(self, self.phy, clk_freq)

misoclib/com/uart/software/wishbone.py

@@ -7,7 +7,7 @@ def write_b(uart, data):
     uart.write(pack('B', data))
 
 
-class LiteScopeUART2WishboneDriver:
+class UARTWishboneBridgeDriver:
     cmds = {
         "write": 0x01,
         "read":  0x02

misoclib/mem/litesata/example_designs/targets/bist.py

@@ -6,10 +6,11 @@ from migen.bank.description import *
 from misoclib.soc import SoC
 
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
+from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+
 from misoclib.mem.litesata.common import *
 from misoclib.mem.litesata.phy import LiteSATAPHY
 from misoclib.mem.litesata import LiteSATA
@@ -99,7 +100,7 @@ class BISTSoC(SoC, AutoCSR):
             with_identifier=True,
             with_timer=False
         )
-        self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200))
+        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
         self.add_wb_master(self.cpu_or_bridge.wishbone)
         self.submodules.crg = _CRG(platform)
 

misoclib/mem/litesata/example_designs/test/bist.py

@@ -2,7 +2,7 @@ import time
 import argparse
 import random as rand
 from collections import OrderedDict
-from misoclib.tools.litescope.software.driver.uart import LiteScopeUART2WishboneDriver
+from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
 
 KB = 1024
 MB = 1024*KB
@@ -149,7 +149,7 @@ SATA BIST utility.
 
 if __name__ == "__main__":
     args = _get_args()
-    wb = LiteScopeUART2WishboneDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+    wb = UARTWishboneBridgeDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     wb.open()
     # # #
     identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")

misoclib/mem/litesata/example_designs/test/make.py

@@ -19,12 +19,12 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.software.driver.uart import LiteScopeUART2WishboneDriver
+        from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+        wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
-        from misoclib.tools.litescope.software.driver.etherbone import LiteScopeEtherboneDriver
-        wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
+        from misoclib.com.liteth.software.wishbone import LiteETHWishboneDriver
+        wb = LiteETHWishboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
     else:
         ValueError("Invalid bridge {}".format(args.bridge))
 

misoclib/tools/litescope/example_designs/targets/simple.py

@@ -3,11 +3,11 @@ from migen.genlib.io import CRG
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
+from misoclib.tools.litescope.core.port import LiteScopeTerm
 from misoclib.tools.litescope.frontend.io import LiteScopeIO
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
-from misoclib.tools.litescope.core.port import LiteScopeTerm
 
+from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
 
 class LiteScopeSoC(SoC, AutoCSR):
     csr_map = {
@@ -25,7 +25,7 @@ class LiteScopeSoC(SoC, AutoCSR):
             with_identifier=True,
             with_timer=False
         )
-        self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200))
+        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
         self.add_wb_master(self.cpu_or_bridge.wishbone)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 

misoclib/tools/litescope/example_designs/test/make.py

@@ -8,8 +8,6 @@ def _get_args():
     parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
     parser.add_argument("--port", default="2", help="UART port")
     parser.add_argument("--baudrate", default=115200, help="UART baudrate")
-    parser.add_argument("--ip_address", default="192.168.0.42", help="Etherbone  IP address")
-    parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port")
     parser.add_argument("--busword", default=32, help="CSR busword")
 
     parser.add_argument("test", nargs="+", help="specify a test")
@@ -19,13 +17,9 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.software.driver.uart import LiteScopeUART2WishboneDriver
+        from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
-    elif args.bridge == "etherbone":
-        from misoclib.tools.litescope.software.driver.etherbone import LiteScopeEtherboneDriver
-        wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
-    else:
+        wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
         ValueError("Invalid bridge {}".format(args.bridge))
 
     def _import(name):

misoclib/tools/litescope/frontend/wishbone.py

@@ -139,8 +139,3 @@ class LiteScopeWishboneBridge(Module):
                 )
             )
         )
-
-class LiteScopeUART2Wishbone(LiteScopeWishboneBridge):
-    def __init__(self, pads, clk_freq, baudrate=115200):
-        self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
-        LiteScopeWishboneBridge.__init__(self, self.phy, clk_freq)