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integration/soc/add_uart: cleanup.

This commit is contained in:
Florent Kermarrec 2020-03-25 18:53:00 +01:00
parent 5bcf730c77
commit 3f43c6a223
1 changed files with 32 additions and 14 deletions
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28
litex/soc/integration/soc.py
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@ -912,25 +912,42 @@ class LiteXSoC(SoC):
# Add UART -------------------------------------------------------------------------------------
def add_uart(self, name, baudrate=115200, fifo_depth=16):
from litex.soc.cores import uart
# Stub / Stream
if name in ["stub", "stream"]:
self.submodules.uart = uart.UART(tx_fifo_depth=0, rx_fifo_depth=0)
if name == "stub":
self.comb += self.uart.sink.ready.eq(1)
elif name == "bridge":
# Bridge
elif name in ["bridge"]:
self.submodules.uart = uart.UARTWishboneBridge(
pads = self.platform.request("serial"),
clk_freq = self.sys_clk_freq,
baudrate = baudrate)
self.bus.add_master(name="uart_bridge", master=self.uart.wishbone)
elif name == "crossover":
# Crossover
elif name in ["crossover"]:
self.submodules.uart = uart.UARTCrossover()
else:
if name == "jtag_atlantic":
# JTAG Atlantic
elif name in ["jtag_atlantic"]:
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif name == "jtag_uart":
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth))
# JTAG UART
elif name in ["jtag_uart"]:
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=self.platform.device)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth))
# Classic UART
else:
self.submodules.uart_phy = uart.UARTPHY(
pads = self.platform.request(name),
@ -939,6 +956,7 @@ class LiteXSoC(SoC):
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth))
self.csr.add("uart_phy", use_loc_if_exists=True)
self.csr.add("uart", use_loc_if_exists=True)
self.irq.add("uart", use_loc_if_exists=True)