Do not use super()

migen/actorlib/dma_asmi.py

@@ -6,7 +6,7 @@ class SequentialReader(Actor):
 	def __init__(self, port):
 		self.port = port
 		assert(len(self.port.slots) == 1)
-		super().__init__(
+		Actor.__init__(self,
 			("address", Sink, [("a", self.port.hub.aw)]),
 			("data", Source, [("d", self.port.hub.dw)]))
 	
@@ -48,7 +48,7 @@ class OOOReader(Actor):
 	def __init__(self, port):
 		self.port = port
 		assert(len(self.port.slots) > 1)
-		super().__init__(
+		Actor.__init__(self,
 			("address", Sink, [("a", self.port.hub.aw)]),
 			("data", Source, [("d", self.port.hub.dw)]))
 	

migen/actorlib/dma_wishbone.py

@@ -5,7 +5,7 @@ from migen.flow.actor import *
 class Reader(Actor):
 	def __init__(self):
 		self.bus = wishbone.Interface()
-		super().__init__(
+		Actor.__init__(self,
 			("address", Sink, [("a", 30)]),
 			("data", Source, [("d", 32)]))
 	
@@ -41,7 +41,7 @@ class Reader(Actor):
 class Writer(Actor):
 	def __init__(self):
 		self.bus = wishbone.Interface()
-		super().__init__(
+		Actor.__init__(self,
 			("address_data", Sink, [("a", 30), ("d", 32)]))
 
 	def get_fragment(self):

migen/actorlib/misc.py

@@ -14,7 +14,7 @@ class IntSequence(Actor):
 		if self.offsetbits:
 			parameters_layout.append(("offset", self.offsetbits))
 		
-		super().__init__(
+		Actor.__init__(self,
 			("parameters", Sink, parameters_layout),
 			("source", Source, [("value", max(self.nbits, self.offsetbits))]))
 	

migen/actorlib/sim.py

@@ -72,7 +72,7 @@ class TokenExchanger(PureSimulable):
 
 class SimActor(Actor):
 	def __init__(self, generator, *endpoint_descriptions, **misc):
-		super().__init__(*endpoint_descriptions, **misc)
+		Actor.__init__(self, *endpoint_descriptions, **misc)
 		self.token_exchanger = TokenExchanger(generator, self)
 	
 	def update_busy(self, s):
@@ -92,5 +92,5 @@ class Dumper(SimActor):
 				else:
 					s = str(list(t.value.values())[0])
 				print(prefix + s)
-		super().__init__(dumper_gen(),
+		SimActor.__init__(self, dumper_gen(),
 			("result", Sink, layout))

migen/actorlib/spi.py

@@ -50,7 +50,7 @@ def _create_registers_assign(layout, target, atomic, prefix=""):
 class SingleGenerator(Actor):
 	def __init__(self, layout, mode):
 		self._mode = mode
-		super().__init__(("source", Source, _convert_layout(layout)))
+		Actor.__init__(self, ("source", Source, _convert_layout(layout)))
 		self._registers, self._assigns = _create_registers_assign(layout,
 			self.token("source"), self._mode != MODE_SINGLE_SHOT)
 		if mode == MODE_EXTERNAL:
@@ -81,7 +81,7 @@ class SingleGenerator(Actor):
 
 class Collector(Actor):
 	def __init__(self, layout, depth=1024):
-		super().__init__(("sink", Sink, layout))
+		Actor.__init__(self, ("sink", Sink, layout))
 		self._depth = depth
 		self._dw = sum(len(s) for s in self.token("sink").flatten())
 		

migen/actorlib/structuring.py

@@ -9,7 +9,7 @@ def _rawbits_layout(l):
 
 class Cast(CombinatorialActor):
 	def __init__(self, layout_from, layout_to):
-		super().__init__(
+		CombinatorialActor.__init__(self,
 			("sink", Sink, _rawbits_layout(layout_from)),
 			("source", Source, _rawbits_layout(layout_to)))
 	
@@ -28,7 +28,7 @@ def pack_layout(l, n):
 class Unpack(Actor):
 	def __init__(self, n, layout_to):
 		self.n = n
-		super().__init__(
+		Actor.__init__(self,
 			("sink", Sink, pack_layout(layout_to, n)),
 			("source", Source, layout_to))
 	
@@ -58,7 +58,7 @@ class Unpack(Actor):
 class Pack(Actor):
 	def __init__(self, layout_from, n):
 		self.n = n
-		super().__init__(
+		Actor.__init__(self,
 			("sink", Sink, layout_from),
 			("source", Source, pack_layout(layout_from, n)))
 	

migen/bank/description.py

@@ -40,7 +40,7 @@ class RegisterFields:
 class RegisterField(RegisterFields):
 	def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False):
 		self.field = Field(name, size, access_bus, access_dev, reset, atomic_write)
-		super().__init__(name, [self.field])
+		RegisterFields.__init__(self, name, [self.field])
 
 (ALIAS_NON_ATOMIC, ALIAS_ATOMIC_HOLD, ALIAS_ATOMIC_COMMIT) = range(3)
 

migen/bus/csr.py

@@ -8,7 +8,7 @@ data_width = 8
 
 class Interface(SimpleInterface):
 	def __init__(self):
-		super().__init__(Description(
+		SimpleInterface.__init__(self, Description(
 			(M_TO_S,	"adr",		14),
 			(M_TO_S,	"we",		1),
 			(M_TO_S,	"dat_w",	data_width),

migen/bus/wishbone.py

@@ -21,11 +21,11 @@ _desc = Description(
 
 class Interface(SimpleInterface):
 	def __init__(self):
-		super().__init__(_desc)
+		SimpleInterface.__init__(self, _desc)
 
 class InterconnectPointToPoint(SimpleInterconnect):
 	def __init__(self, master, slave):
-		super().__init__(master, [slave])
+		SimpleInterconnect.__init__(self, master, [slave])
 
 class Arbiter:
 	def __init__(self, masters, target):

migen/fhdl/structure.py

@@ -105,35 +105,35 @@ class Value(HUID):
 		return _Assign(self, r)
 	
 	def __hash__(self):
-		return super().__hash__()
+		return HUID.__hash__(self)
 
 class _Operator(Value):
 	def __init__(self, op, operands):
-		super().__init__()
+		Value.__init__(self)
 		self.op = op
 		self.operands = operands
 
 class _Slice(Value):
 	def __init__(self, value, start, stop):
-		super().__init__()
+		Value.__init__(self)
 		self.value = value
 		self.start = start
 		self.stop = stop
 
 class Cat(Value):
 	def __init__(self, *args):
-		super().__init__()
+		Value.__init__(self)
 		self.l = args
 
 class Replicate(Value):
 	def __init__(self, v, n):
-		super().__init__()
+		Value.__init__(self)
 		self.v = v
 		self.n = n
 
 class Signal(Value):
 	def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None):
-		super().__init__()
+		Value.__init__(self)
 		
 		# determine number of bits and signedness
 		if bits_sign is None:
@@ -227,13 +227,13 @@ class Array(list):
 		if isinstance(key, Value):
 			return _ArrayProxy(self, key)
 		else:
-			return super().__getitem__(key)
+			return list.__getitem__(self, key)
 
 # extras
 
 class Instance(HUID):
 	def __init__(self, of, *items, name=""):
-		super().__init__()
+		HUID.__init__(self)
 		self.of = of
 		if name:
 			self.name_override = name
@@ -292,7 +292,7 @@ class _MemoryPort:
 
 class Memory(HUID):
 	def __init__(self, width, depth, init=None):
-		super().__init__()
+		HUID.__init__(self)
 		self.width = width
 		self.depth = depth
 		self.ports = []

migen/fhdl/tools.py

@@ -191,7 +191,7 @@ class _ArrayLowerer(NodeTransformer):
 				cases[n] = [assign]
 			return Case(k, cases).makedefault()
 		else:
-			return super().visit_Assign(node)
+			return NodeTransformer.visit_Assign(self, node)
 	
 	def visit_ArrayProxy(self, node):
 		array_muxed = Signal(value_bits_sign(node))

migen/flow/actor.py

@@ -34,7 +34,7 @@ class Source(Endpoint):
 
 class Actor(HUID):
 	def __init__(self, *endpoint_descriptions, endpoints=None):
-		super().__init__()
+		HUID.__init__(self)
 		if endpoints is None:
 			self.endpoints = {}
 			for desc in endpoint_descriptions:
@@ -109,7 +109,7 @@ class SequentialActor(BinaryActor):
 	def __init__(self, delay, *endpoint_descriptions, **misc):
 		self.delay = delay
 		self.trigger = Signal()
-		super().__init__(*endpoint_descriptions, **misc)
+		BinaryActor.__init__(self, *endpoint_descriptions, **misc)
 
 	def get_binary_control_fragment(self, stb_i, ack_o, stb_o, ack_i):
 		ready = Signal()
@@ -141,7 +141,7 @@ class PipelinedActor(BinaryActor):
 	def __init__(self, latency, *endpoint_descriptions, **misc):
 		self.latency = latency
 		self.pipe_ce = Signal()
-		super().__init__(*endpoint_descriptions, **misc)
+		BinaryActor.__init__(self, *endpoint_descriptions, **misc)
 
 	def get_binary_control_fragment(self, stb_i, ack_o, stb_o, ack_i):
 		valid = Signal(self.latency)

migen/flow/isd.py

@@ -64,7 +64,7 @@ class DFGReporter(DFGHook):
 		self._r_reset = RegisterRaw("reset", 1)
 		
 		self.order = []
-		super().__init__(dfg, self._create)
+		DFGHook.__init__(self, dfg, self._create)
 	
 	def _create(self, u, ep, v):
 		self.order.append((u, ep, v))
@@ -92,4 +92,4 @@ class DFGReporter(DFGHook):
 				h.freeze.eq(self._r_freeze.field.r),
 				h.reset.eq(self._r_reset.re)
 			]
-		return Fragment(comb) + super().get_fragment()
+		return Fragment(comb) + DFGHook.get_fragment(self)

migen/flow/network.py

@@ -12,7 +12,7 @@ from migen.flow.isd import DFGReporter
 
 class AbstractActor(HUID):
 	def __init__(self, actor_class, parameters=dict(), name=None):
-		super().__init__()
+		HUID.__init__(self)
 		self.actor_class = actor_class
 		self.parameters = parameters
 		self.name = name
@@ -29,7 +29,7 @@ class AbstractActor(HUID):
 
 class DataFlowGraph(MultiDiGraph):
 	def __init__(self):
-		super().__init__()
+		MultiDiGraph.__init__(self)
 		self.elaborated = False
 	
 	def add_connection(self, source_node, sink_node,
@@ -209,7 +209,7 @@ class CompositeActor(Actor):
 		self.dfg = dfg
 		if debugger:
 			self.debugger = DFGReporter(self.dfg, debugger_nbits)
-		super().__init__()
+		Actor.__init__(self)
 	
 	def get_registers(self):
 		if hasattr(self, "debugger"):

migen/flow/perftools.py

@@ -2,7 +2,7 @@ from migen.flow.hooks import *
 
 class EndpointReporter(EndpointSimHook):
 	def __init__(self, endpoint):
-		super().__init__(endpoint)
+		EndpointSimHook.__init__(self, endpoint)
 		self.reset()
 	
 	def reset(self):
@@ -39,7 +39,7 @@ class EndpointReporter(EndpointSimHook):
 
 class DFGReporter(DFGHook):
 	def __init__(self, dfg):
-		super().__init__(dfg, lambda u, ep, v: EndpointReporter(u.actor.endpoints[ep]))
+		DFGHook.__init__(self, dfg, lambda u, ep, v: EndpointReporter(u.actor.endpoints[ep]))
 
 	def get_edge_labels(self):
 		d = dict()

migen/flow/plumbing.py

@@ -5,7 +5,7 @@ from migen.corelogic.misc import optree
 
 class Buffer(PipelinedActor):
 	def __init__(self, layout):
-		super().__init__(1,
+		PipelinedActor.__init__(self, 1,
 			("d", Sink, layout), ("q", Source, layout))
 	
 	def get_process_fragment(self):
@@ -22,7 +22,7 @@ class Combinator(Actor):
 			for n, r in enumerate(subrecords)]
 		ep_source = ("source", Source, source)
 		eps.append(ep_source)
-		super().__init__(*eps)
+		Actor.__init__(self, *eps)
 
 	def get_fragment(self):
 		source = self.endpoints["source"]
@@ -45,7 +45,7 @@ class Splitter(Actor):
 			for n, r in enumerate(subr)]
 		ep_sink = ("sink", Sink, sink)
 		eps.append(ep_sink)
-		super().__init__(*eps)
+		Actor.__init__(self, *eps)
 		
 	def get_fragment(self):
 		sources = [self.endpoints[e] for e in self.sources()]

migen/pytholite/io.py

@@ -12,18 +12,18 @@ from migen.pytholite.expr import ExprCompiler
 
 class Pytholite(UnifiedIOObject):
 	def __init__(self, dataflow=None, buses={}):
-		super().__init__(dataflow, buses)
+		UnifiedIOObject.__init__(self, dataflow, buses)
 		if dataflow is not None:
 			self.busy.reset = 1
 		self.memory_ports = dict((mem, mem.get_port(write_capable=True, we_granularity=8))
 			for mem in self._memories)
 	
 	def get_fragment(self):
-		return super().get_fragment() + self.fragment
+		return UnifiedIOObject.get_fragment(self) + self.fragment
 
 class _TokenPullExprCompiler(ExprCompiler):
 	def __init__(self, symdict, modelname, ep):
-		super().__init__(symdict)
+		ExprCompiler.__init__(self, symdict)
 		self.modelname = modelname
 		self.ep = ep
 	
@@ -85,7 +85,7 @@ def _gen_df_io(compiler, modelname, to_model, from_model):
 
 class _BusReadExprCompiler(ExprCompiler):
 	def __init__(self, symdict, modelname, data_signal):
-		super().__init__(symdict)
+		ExprCompiler.__init__(self, symdict)
 		self.modelname = modelname
 		self.data_signal = data_signal
 	

migen/uio/ioo.py

@@ -9,7 +9,7 @@ from migen.uio.trampoline import Trampoline
 class UnifiedIOObject(Actor):
 	def __init__(self, dataflow=None, buses={}):
 		if dataflow is not None:
-			super().__init__(*dataflow)
+			Actor.__init__(self, *dataflow)
 		self.buses = buses
 		self._memories = set(v for v in self.buses.values() if isinstance(v, Memory))
 	
@@ -21,7 +21,7 @@ class UnifiedIOObject(Actor):
 class UnifiedIOSimulation(UnifiedIOObject):
 	def __init__(self, generator, dataflow=None, buses={}):
 		self.generator = Trampoline(generator)
-		super().__init__(dataflow, buses)
+		UnifiedIOObject.__init__(self, dataflow, buses)
 		
 		self.callers = []
 		self.busname_to_caller_id = {}
@@ -76,5 +76,5 @@ class UnifiedIOSimulation(UnifiedIOObject):
 				yield None
 	
 	def get_fragment(self):
-		f = super().get_fragment()
+		f = UnifiedIOObject.get_fragment(self)
 		return sum([c.get_fragment() for c in self.callers], f)