cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite.
This commit is contained in:
Florent Kermarrec
parent
2a5a7536b8
commit
3fb99b7d33
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@ -19,13 +19,16 @@ from litex.soc.cores.spi import SPIMaster
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# SpiFlash Quad/Dual/Single (memory-mapped) --------------------------------------------------------
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_QIOFR = 0xeb
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_QIOPP = 0x12
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_FAST_READ = 0x0b
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_DIOFR = 0xbb
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_QIOFR = 0xeb
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_QIOPP = 0x12
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def _format_cmd(cmd, spi_width):
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"""
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`cmd` is the read instruction. Since everything is transmitted on all
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dq lines (cmd, adr and data), we need to reformat cmd in single spi mode.
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dq lines (cmd, adr and data), extend/interleave cmd to full pads.dq
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width even if dq1-dq3 are don't care during the command phase:
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For example, for N25Q128, 0xeb is the quad i/o fast read, and
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extended to 4 bits (dq1,dq2,dq3 high) is: 0xfffefeff
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"""
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@ -78,8 +81,272 @@ class SpiFlashCommon(Module):
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if hasattr(self, "clk_primitive_needed"):
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assert self.clk_primitive_registered == True
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class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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Simple SPI flash.
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Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
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Read). Only supports mode3 (cpol=1, cpha=1).
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"""
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SpiFlashCommon.__init__(self, pads)
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self.bus = bus = wishbone.Interface()
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spi_width = len(pads.dq)
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assert spi_width >= 2
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if with_bitbang:
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self.bitbang = CSRStorage(4, reset_less=True, fields=[
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CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
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("0", "OUT", "SPI pins are all output"),
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("1", "IN", "SPI pins are all input"),
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])
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], description="""
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Bitbang controls for SPI output. Only standard 1x SPI is supported, and as
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a result all four wires are ganged together. This means that it is only possible
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to perform half-duplex operations, using this SPI core.
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""")
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self.miso = CSRStatus(description="Incoming value of MISO signal.")
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self.bitbang_en = CSRStorage(description="Write a ``1`` here to disable memory-mapped mode and enable bitbang mode.")
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# # #
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cs_n = Signal(reset=1)
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clk = Signal()
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dq_oe = Signal()
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wbone_width = len(bus.dat_r)
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read_cmd_params = {
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4: (_format_cmd(_QIOFR, 4), 4*8),
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2: (_format_cmd(_DIOFR, 2), 2*8),
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1: (_format_cmd(_FAST_READ, 1), 1*8)
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}
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read_cmd, cmd_width = read_cmd_params[spi_width]
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addr_width = 24
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dq = TSTriple(spi_width)
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# Keep DQ2,DQ3 as outputs during bitbang, this ensures they activate ~WP or ~HOLD functions
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self.specials.dq0 = Tristate(pads.dq[0], o=dq.o[0], i=dq.i[0], oe=dq.oe)
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self.specials.dq1 = Tristate(pads.dq[1], o=dq.o[1], i=dq.i[1], oe=dq.oe)
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self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=(dq.oe | self.bitbang_en.storage))
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self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=(dq.oe | self.bitbang_en.storage))
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sr = Signal(max(cmd_width, addr_width, wbone_width))
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if endianness == "big":
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self.comb += bus.dat_r.eq(sr)
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else:
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self.comb += bus.dat_r.eq(reverse_bytes(sr))
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hw_read_logic = [
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pads.clk.eq(clk),
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pads.cs_n.eq(cs_n),
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dq.o.eq(sr[-spi_width:]),
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dq.oe.eq(dq_oe)
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]
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if with_bitbang:
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bitbang_logic = [
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pads.clk.eq(self.bitbang.storage[1]),
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pads.cs_n.eq(self.bitbang.storage[2]),
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# In Dual/Quad mode, no single data pin is consistently
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# an input or output thanks to dual/quad reads, so we need a bit
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# to swap direction of the pins. Aside from this additional bit,
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# bitbang mode is identical for Single/Dual/Quad; dq[0] is mosi
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# and dq[1] is miso, meaning remaining data pin values don't
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# appear in CSR registers.
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If(self.bitbang.storage[3],
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dq.oe.eq(0)
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).Else(
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dq.oe.eq(1)
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),
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If(self.bitbang.storage[1], # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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self.miso.status.eq(dq.i[1])
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),
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dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))
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]
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self.comb += [
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If(self.bitbang_en.storage,
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bitbang_logic
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).Else(
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hw_read_logic
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)
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]
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else:
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self.comb += hw_read_logic
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if div < 2:
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raise ValueError("Unsupported value \'{}\' for div parameter for SpiFlash core".format(div))
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else:
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i = Signal(max=div)
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dqi = Signal(spi_width)
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self.sync += [
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If(i == div//2 - 1,
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clk.eq(1),
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dqi.eq(dq.i),
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),
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If(i == div - 1,
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i.eq(0),
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clk.eq(0),
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sr.eq(Cat(dqi, sr[:-spi_width]))
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).Else(
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i.eq(i + 1),
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),
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]
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# spi is byte-addressed, prefix by zeros
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z = Replicate(0, log2_int(wbone_width//8))
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seq = [
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(cmd_width//spi_width*div,
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[dq_oe.eq(1), cs_n.eq(0), sr[-cmd_width:].eq(read_cmd)]),
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(addr_width//spi_width*div,
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[sr[-addr_width:].eq(Cat(z, bus.adr))]),
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((dummy + wbone_width//spi_width)*div,
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[dq_oe.eq(0)]),
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(1,
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[bus.ack.eq(1), cs_n.eq(1)]),
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(div, # tSHSL!
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[bus.ack.eq(0)]),
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(0,
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[]),
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]
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# accumulate timeline deltas
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t, tseq = 0, []
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for dt, a in seq:
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tseq.append((t, a))
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t += dt
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self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
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class SpiFlashSingle(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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Simple memory-mapped SPI flash.
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Supports 1-bit reads. Only supports mode3 (cpol=1, cpha=1).
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"""
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SpiFlashCommon.__init__(self, pads)
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self.bus = bus = wishbone.Interface()
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if with_bitbang:
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self.bitbang = CSRStorage(4, reset_less=True, fields=[
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CSRField("mosi", description="Output value for SPI MOSI pin."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Unused in this design.")
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], description="""Bitbang controls for SPI output.""")
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self.miso = CSRStatus(description="Incoming value of MISO pin.")
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self.bitbang_en = CSRStorage(description="Write a ``1`` here to disable memory-mapped mode and enable bitbang mode.")
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# # #
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if hasattr(pads, "wp"):
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self.comb += pads.wp.eq(1)
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if hasattr(pads, "hold"):
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self.comb += pads.hold.eq(1)
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cs_n = Signal(reset=1)
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clk = Signal()
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wbone_width = len(bus.dat_r)
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read_cmd = _FAST_READ
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cmd_width = 8
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addr_width = 24
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sr = Signal(max(cmd_width, addr_width, wbone_width))
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if endianness == "big":
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self.comb += bus.dat_r.eq(sr)
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else:
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self.comb += bus.dat_r.eq(reverse_bytes(sr))
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hw_read_logic = [
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pads.clk.eq(clk),
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pads.cs_n.eq(cs_n),
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pads.mosi.eq(sr[-1:])
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]
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if with_bitbang:
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bitbang_logic = [
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pads.clk.eq(self.bitbang.storage[1]),
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pads.cs_n.eq(self.bitbang.storage[2]),
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If(self.bitbang.storage[1], # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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self.miso.status.eq(pads.miso)
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),
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pads.mosi.eq(self.bitbang.storage[0])
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]
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self.comb += [
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If(self.bitbang_en.storage,
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bitbang_logic
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).Else(
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hw_read_logic
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)
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]
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else:
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self.comb += hw_read_logic
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if div < 2:
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raise ValueError("Unsupported value \'{}\' for div parameter for SpiFlash core".format(div))
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else:
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i = Signal(max=div)
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miso = Signal()
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self.sync += [
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If(i == div//2 - 1,
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clk.eq(1),
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miso.eq(pads.miso),
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),
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If(i == div - 1,
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i.eq(0),
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clk.eq(0),
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sr.eq(Cat(miso, sr[:-1]))
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).Else(
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i.eq(i + 1),
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),
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]
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# spi is byte-addressed, prefix by zeros
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z = Replicate(0, log2_int(wbone_width//8))
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seq = [
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(cmd_width*div,
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[cs_n.eq(0), sr[-cmd_width:].eq(read_cmd)]),
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(addr_width*div,
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[sr[-addr_width:].eq(Cat(z, bus.adr))]),
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((dummy + wbone_width)*div,
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[]),
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(1,
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[bus.ack.eq(1), cs_n.eq(1)]),
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(div, # tSHSL!
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[bus.ack.eq(0)]),
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(0,
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[]),
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]
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# accumulate timeline deltas
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t, tseq = 0, []
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for dt, a in seq:
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tseq.append((t, a))
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t += dt
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self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
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def SpiFlash(pads, *args, **kwargs):
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if hasattr(pads, "mosi"):
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return SpiFlashSingle(pads, *args, **kwargs)
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else:
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return SpiFlashDualQuad(pads, *args, **kwargs)
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# SpiFlash Quad Read/Write (memory-mapped) ---------------------------------------------------------
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class SpiFlashQuadReadWrite(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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Simple SPI flash.
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@ -137,7 +404,7 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
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self.specials.dq0 = Tristate(pads.dq[0], o=dq.o[0], i=dq.i[0], oe=dq.oe)
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self.specials.dq1 = Tristate(pads.dq[1], o=dq.o[1], i=dq.i[1], oe=dq.oe)
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if with_bitbang:
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# Keep DQ2,DQ3 as outputs during bitbang, this ensures they activate ~WP or ~HOLD functions
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# Keep DQ2,DQ3 as outputs during bitbang, this ensures they activate ~WP or ~HOLD functions
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self.specials.dq2 = Tristate(pads.dq[2], o=dq.o[2], i=dq.i[2], oe=(dq.oe | self.bitbang_en.storage))
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self.specials.dq3 = Tristate(pads.dq[3], o=dq.o[3], i=dq.i[3], oe=(dq.oe | self.bitbang_en.storage))
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else:
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@ -284,7 +551,7 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
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# write data to sr
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self.sync += If(queue.status[2] & (i == div - 1) & ~self.en_quad.storage[0],
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sr[-max_transfer_size:].eq(self.spi_in.storage), queue.status[2].eq(0), queue.status[3].eq(1), cs_n.eq(0), dq_oe.eq(1))
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sr[-max_transfer_size:].eq(self.spi_in.storage), queue.status[2].eq(0), queue.status[3].eq(1), cs_n.eq(0), dq_oe.eq(1))
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# count spi to slave transfer cycles
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self.sync += If(queue.status[3] & (self.in_left > 0) & (i == div - 1), self.in_left.eq(self.in_left - 1), dq_oe.eq(1))
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@ -309,127 +576,6 @@ class SpiFlashDualQuad(SpiFlashCommon, AutoCSR):
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self.sync += timeline(queue.status[0] & ~self.en_quad.storage[0] & (i == div - 1), accumulate_timeline_deltas(read_seq))
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self.sync += timeline(queue.status[1] & ~self.en_quad.storage[0] & (i == div - 1), accumulate_timeline_deltas(write_seq))
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class SpiFlashSingle(SpiFlashCommon, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True, endianness="big"):
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"""
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Simple memory-mapped SPI flash.
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Supports 1-bit reads. Only supports mode3 (cpol=1, cpha=1).
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"""
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SpiFlashCommon.__init__(self, pads)
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self.bus = bus = wishbone.Interface()
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if with_bitbang:
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self.bitbang = CSRStorage(4, reset_less=True, fields=[
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CSRField("mosi", description="Output value for SPI MOSI pin."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Unused in this design.")
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], description="""Bitbang controls for SPI output.""")
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self.miso = CSRStatus(description="Incoming value of MISO pin.")
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self.bitbang_en = CSRStorage(description="Write a ``1`` here to disable memory-mapped mode and enable bitbang mode.")
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# # #
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if hasattr(pads, "wp"):
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self.comb += pads.wp.eq(1)
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if hasattr(pads, "hold"):
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self.comb += pads.hold.eq(1)
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cs_n = Signal(reset=1)
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clk = Signal()
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wbone_width = len(bus.dat_r)
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read_cmd = _FAST_READ
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cmd_width = 8
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addr_width = 24
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sr = Signal(max(cmd_width, addr_width, wbone_width))
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if endianness == "big":
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self.comb += bus.dat_r.eq(sr)
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else:
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self.comb += bus.dat_r.eq(reverse_bytes(sr))
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hw_read_logic = [
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pads.clk.eq(clk),
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pads.cs_n.eq(cs_n),
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pads.mosi.eq(sr[-1:])
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]
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if with_bitbang:
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bitbang_logic = [
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pads.clk.eq(self.bitbang.storage[1]),
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pads.cs_n.eq(self.bitbang.storage[2]),
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If(self.bitbang.storage[1], # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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self.miso.status.eq(pads.miso)
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),
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pads.mosi.eq(self.bitbang.storage[0])
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]
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self.comb += [
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If(self.bitbang_en.storage,
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bitbang_logic
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).Else(
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hw_read_logic
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)
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]
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else:
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self.comb += hw_read_logic
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if div < 2:
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raise ValueError("Unsupported value \'{}\' for div parameter for SpiFlash core".format(div))
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else:
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i = Signal(max=div)
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miso = Signal()
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self.sync += [
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If(i == div//2 - 1,
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clk.eq(1),
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miso.eq(pads.miso),
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),
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If(i == div - 1,
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i.eq(0),
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clk.eq(0),
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sr.eq(Cat(miso, sr[:-1]))
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).Else(
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i.eq(i + 1),
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),
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]
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# spi is byte-addressed, prefix by zeros
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z = Replicate(0, log2_int(wbone_width//8))
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seq = [
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(cmd_width*div,
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[cs_n.eq(0), sr[-cmd_width:].eq(read_cmd)]),
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(addr_width*div,
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[sr[-addr_width:].eq(Cat(z, bus.adr))]),
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((dummy + wbone_width)*div,
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[]),
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(1,
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[bus.ack.eq(1), cs_n.eq(1)]),
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(div, # tSHSL!
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[bus.ack.eq(0)]),
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(0,
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[]),
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]
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# accumulate timeline deltas
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t, tseq = 0, []
|
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for dt, a in seq:
|
||||
tseq.append((t, a))
|
||||
t += dt
|
||||
|
||||
self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
|
||||
|
||||
|
||||
def SpiFlash(pads, *args, **kwargs):
|
||||
if hasattr(pads, "mosi"):
|
||||
return SpiFlashSingle(pads, *args, **kwargs)
|
||||
else:
|
||||
return SpiFlashDualQuad(pads, *args, **kwargs)
|
||||
|
||||
# Xilinx 7-Series FPGAs SPI Flash (non-memory-mapped) ----------------------------------------------
|
||||
|
||||
class S7SPIFlash(Module, AutoCSR):
|
||||
|
|
|
|||
Loading…
Reference in New Issue