Merge pull request #541 from antmicro/jboc/spd-read
Add support for I2C to read SPD EEPROM
This commit is contained in:
enjoy-digital
GitHub
commit
3fd6ecd86e
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@ -17,6 +17,7 @@ OBJECTS = isr.o \
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cmd_bios.o \
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cmd_mem.o \
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cmd_boot.o \
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cmd_i2c.o \
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cmd_spiflash.o \
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cmd_litedram.o \
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cmd_liteeth.o \
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@ -0,0 +1,121 @@
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// SPDX-License-Identifier: BSD-Source-Code
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <generated/csr.h>
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#include <i2c.h>
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#include "../command.h"
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#include "../helpers.h"
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/**
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* Command "i2creset"
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*
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* Reset I2C line state in case a slave locks the line.
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*
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*/
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#ifdef CSR_I2C_BASE
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define_command(i2creset, i2c_reset, "Reset I2C line state", I2C_CMDS);
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#endif
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/**
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* Command "i2cwr"
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*
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* Write I2C slave memory using 7-bit slave address and 8-bit memory address.
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*
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*/
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#ifdef CSR_I2C_BASE
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static void i2cwr_handler(int nb_params, char **params)
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{
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int i;
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char *c;
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unsigned char write_params[32]; // also indirectly limited by CMD_LINE_BUFFER_SIZE
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if (nb_params < 2) {
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printf("i2cwr <slaveaddr7bit> <addr> [<data>, ...]");
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return;
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}
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if (nb_params - 1 > sizeof(write_params)) {
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printf("Max data length is %d", sizeof(write_params));
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return;
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}
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for (i = 0; i < nb_params; ++i) {
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write_params[i] = strtoul(params[i], &c, 0);
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if (*c != 0) {
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printf("Incorrect value of parameter %d", i);
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return;
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}
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}
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if (!i2c_write(write_params[0], write_params[1], &write_params[2], nb_params - 2)) {
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printf("Error during I2C write");
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return;
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}
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}
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define_command(i2cwr, i2cwr_handler, "Write over I2C", I2C_CMDS);
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#endif
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/**
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* Command "i2crd"
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*
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* Read I2C slave memory using 7-bit slave address and 8-bit memory address.
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*
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*/
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#ifdef CSR_I2C_BASE
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static void i2crd_handler(int nb_params, char **params)
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{
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char *c;
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int len;
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unsigned char slave_addr, addr;
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unsigned char buf[256];
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bool send_stop = true;
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if (nb_params < 3) {
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printf("i2crd <slaveaddr7bit> <addr> <len> [<send_stop>]");
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return;
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}
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slave_addr = strtoul(params[0], &c, 0);
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if (*c != 0) {
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printf("Incorrect slave address");
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return;
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}
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addr = strtoul(params[1], &c, 0);
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if (*c != 0) {
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printf("Incorrect memory address");
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return;
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}
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len = strtoul(params[2], &c, 0);
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if (*c != 0) {
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printf("Incorrect data length");
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return;
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}
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if (len > sizeof(buf)) {
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printf("Max data count is %d", sizeof(buf));
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return;
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}
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if (nb_params > 3) {
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send_stop = strtoul(params[3], &c, 0) != 0;
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if (*c != 0) {
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printf("Incorrect send_stop value");
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return;
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}
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}
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if (!i2c_read(slave_addr, addr, buf, len, send_stop)) {
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printf("Error during I2C read");
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return;
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}
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dump_bytes((unsigned int *) buf, len, addr);
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}
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define_command(i2crd, i2crd_handler, "Read over I2C", I2C_CMDS);
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#endif
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@ -2,8 +2,10 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <generated/csr.h>
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#include <i2c.h>
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#include <liblitedram/sdram.h>
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@ -221,3 +223,55 @@ define_command(sdrlevel, sdrlevel, "Perform read/write leveling", LITEDRAM_CMDS)
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#ifdef CSR_SDRAM_BASE
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define_command(memtest, memtest, "Run a memory test", LITEDRAM_CMDS);
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#endif
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/**
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* Command "spdread"
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*
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* Read contents of SPD EEPROM memory.
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* SPD address is a 3-bit address defined by the pins A0, A1, A2.
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*
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*/
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#ifdef CSR_I2C_BASE
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#define SPD_RW_PREAMBLE 0b1010
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#define SPD_RW_ADDR(a210) ((SPD_RW_PREAMBLE << 3) | ((a210) & 0b111))
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static void spdread_handler(int nb_params, char **params)
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{
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char *c;
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unsigned char spdaddr;
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unsigned char buf[256];
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int len = sizeof(buf);
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bool send_stop = true;
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if (nb_params < 1) {
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printf("spdread <spdaddr> [<send_stop>]");
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return;
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}
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spdaddr = strtoul(params[0], &c, 0);
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if (*c != 0) {
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printf("Incorrect address");
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return;
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}
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if (spdaddr > 0b111) {
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printf("SPD EEPROM max address is 0b111 (defined by A0, A1, A2 pins)");
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return;
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}
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if (nb_params > 1) {
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send_stop = strtoul(params[1], &c, 0) != 0;
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if (*c != 0) {
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printf("Incorrect send_stop value");
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return;
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}
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}
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if (!i2c_read(SPD_RW_ADDR(spdaddr), 0, buf, len, send_stop)) {
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printf("Error when reading SPD EEPROM");
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return;
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}
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dump_bytes((unsigned int *) buf, len, 0);
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}
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define_command(spdread, spdread_handler, "Read SPD EEPROM", LITEDRAM_CMDS);
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#endif
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@ -15,6 +15,7 @@
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#define MEM_CMDS 3
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#define BOOT_CMDS 3
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#define SPIFLASH_CMDS 4
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#define I2C_CMDS 4
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#define LITEDRAM_CMDS 4
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#define LITEETH_CMDS 5
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#define LITESDCARD_CMDS 7
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@ -0,0 +1,26 @@
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#ifndef __I2C_H
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#define __I2C_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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/* I2C frequency defaults to a safe value in range 10-100 kHz to be compatible with SMBus */
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#ifndef I2C_FREQ_HZ
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#define I2C_FREQ_HZ 50000
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#endif
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#define I2C_ADDR_WR(addr) ((addr) << 1)
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#define I2C_ADDR_RD(addr) (((addr) << 1) | 1u)
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void i2c_reset(void);
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bool i2c_write(unsigned char slave_addr, unsigned char addr, const unsigned char *data, unsigned int len);
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bool i2c_read(unsigned char slave_addr, unsigned char addr, unsigned char *data, unsigned int len, bool send_stop);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __I2C_H */
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@ -2,7 +2,7 @@ include ../include/generated/variables.mak
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include $(SOC_DIRECTORY)/software/common.mak
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OBJECTS = exception.o libc.o errno.o crc16.o crc32.o console.o \
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system.o id.o uart.o time.o qsort.o strtod.o spiflash.o strcasecmp.o
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system.o id.o uart.o time.o qsort.o strtod.o spiflash.o strcasecmp.o i2c.o
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all: crt0-ctr.o crt0-xip.o libbase.a libbase-nofloat.a
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@ -0,0 +1,204 @@
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// This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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#include <i2c.h>
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#include <generated/csr.h>
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#ifdef CSR_I2C_BASE
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#define I2C_PERIOD_CYCLES (CONFIG_CLOCK_FREQUENCY / I2C_FREQ_HZ)
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#define I2C_DELAY(n) cdelay((n)*I2C_PERIOD_CYCLES/4)
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static inline void cdelay(int i)
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{
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while(i > 0) {
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__asm__ volatile(CONFIG_CPU_NOP);
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i--;
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}
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}
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static inline void i2c_oe_scl_sda(bool oe, bool scl, bool sda)
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{
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i2c_w_write(
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((oe & 1) << CSR_I2C_W_OE_OFFSET) |
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((scl & 1) << CSR_I2C_W_SCL_OFFSET) |
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((sda & 1) << CSR_I2C_W_SDA_OFFSET)
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);
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}
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// START condition: 1-to-0 transition of SDA when SCL is 1
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static void i2c_start(void)
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{
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i2c_oe_scl_sda(1, 1, 1);
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I2C_DELAY(1);
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i2c_oe_scl_sda(1, 1, 0);
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I2C_DELAY(1);
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i2c_oe_scl_sda(1, 0, 0);
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I2C_DELAY(1);
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}
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// STOP condition: 0-to-1 transition of SDA when SCL is 1
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static void i2c_stop(void)
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{
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i2c_oe_scl_sda(1, 0, 0);
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I2C_DELAY(1);
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i2c_oe_scl_sda(1, 1, 0);
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I2C_DELAY(1);
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i2c_oe_scl_sda(1, 1, 1);
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I2C_DELAY(1);
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i2c_oe_scl_sda(0, 1, 1);
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}
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// Call when in the middle of SCL low, advances one clk period
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static void i2c_transmit_bit(int value)
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{
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i2c_oe_scl_sda(1, 0, value);
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I2C_DELAY(1);
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i2c_oe_scl_sda(1, 1, value);
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I2C_DELAY(2);
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i2c_oe_scl_sda(1, 0, value);
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I2C_DELAY(1);
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i2c_oe_scl_sda(0, 0, 0); // release line
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}
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// Call when in the middle of SCL low, advances one clk period
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static int i2c_receive_bit(void)
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{
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int value;
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i2c_oe_scl_sda(0, 0, 0);
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I2C_DELAY(1);
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i2c_oe_scl_sda(0, 1, 0);
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I2C_DELAY(1);
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// read in the middle of SCL high
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value = i2c_r_read() & 1;
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I2C_DELAY(1);
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i2c_oe_scl_sda(0, 0, 0);
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I2C_DELAY(1);
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return value;
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}
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// Send data byte and return 1 if slave sends ACK
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static bool i2c_transmit_byte(unsigned char data)
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{
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int i;
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int ack;
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// SCL should have already been low for 1/4 cycle
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i2c_oe_scl_sda(0, 0, 0);
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for (i = 0; i < 8; ++i) {
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// MSB first
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i2c_transmit_bit((data & (1 << 7)) != 0);
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data <<= 1;
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}
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ack = i2c_receive_bit();
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// 0 from slave means ack
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return ack == 0;
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}
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// Read data byte and send ACK if ack=1
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static unsigned char i2c_receive_byte(bool ack)
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{
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int i;
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unsigned char data = 0;
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for (i = 0; i < 8; ++i) {
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data <<= 1;
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data |= i2c_receive_bit();
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}
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i2c_transmit_bit(!ack);
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return data;
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}
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// Reset line state
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void i2c_reset(void)
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{
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int i;
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i2c_oe_scl_sda(1, 1, 1);
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I2C_DELAY(8);
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for (i = 0; i < 9; ++i) {
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i2c_oe_scl_sda(1, 0, 1);
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I2C_DELAY(2);
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i2c_oe_scl_sda(1, 1, 1);
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I2C_DELAY(2);
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}
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i2c_oe_scl_sda(0, 0, 1);
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I2C_DELAY(1);
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i2c_stop();
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i2c_oe_scl_sda(0, 1, 1);
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I2C_DELAY(8);
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}
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/*
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* Read slave memory over I2C starting at given address
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*
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* First writes the memory starting address, then reads the data:
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* START WR(slaveaddr) WR(addr) STOP START WR(slaveaddr) RD(data) RD(data) ... STOP
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* Some chips require that after transmiting the address, there will be no STOP in between:
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* START WR(slaveaddr) WR(addr) START WR(slaveaddr) RD(data) RD(data) ... STOP
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*/
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bool i2c_read(unsigned char slave_addr, unsigned char addr, unsigned char *data, unsigned int len, bool send_stop)
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{
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int i;
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i2c_start();
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if(!i2c_transmit_byte(I2C_ADDR_WR(slave_addr))) {
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i2c_stop();
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return false;
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}
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if(!i2c_transmit_byte(addr)) {
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i2c_stop();
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return false;
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}
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if (send_stop) {
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i2c_stop();
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}
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i2c_start();
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if(!i2c_transmit_byte(I2C_ADDR_RD(slave_addr))) {
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i2c_stop();
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return false;
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}
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for (i = 0; i < len; ++i) {
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data[i] = i2c_receive_byte(i != len - 1);
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}
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i2c_stop();
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return true;
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}
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/*
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* Write slave memory over I2C starting at given address
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*
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* First writes the memory starting address, then writes the data:
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* START WR(slaveaddr) WR(addr) WR(data) WR(data) ... STOP
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*/
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bool i2c_write(unsigned char slave_addr, unsigned char addr, const unsigned char *data, unsigned int len)
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{
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int i;
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i2c_start();
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if(!i2c_transmit_byte(I2C_ADDR_WR(slave_addr))) {
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i2c_stop();
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return false;
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}
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if(!i2c_transmit_byte(addr)) {
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i2c_stop();
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return false;
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}
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for (i = 0; i < len; ++i) {
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if(!i2c_transmit_byte(data[i])) {
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i2c_stop();
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return false;
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}
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}
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i2c_stop();
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return true;
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}
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#endif /* CSR_I2C_BASE */
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@ -20,6 +20,7 @@ from litex.soc.integration.builder import *
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from litex.soc.integration.soc import *
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from litedram import modules as litedram_modules
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from litedram.modules import parse_spd_hexdump
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from litedram.common import *
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from litedram.phy.model import SDRAMPHYModel
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@ -305,7 +306,7 @@ def main():
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parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
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parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
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parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
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parser.add_argument("--sdram-from-spd-data", default=None, help="Generate SDRAM module based on SPD data from file")
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parser.add_argument("--sdram-from-spd-dump", default=None, help="Generate SDRAM module based on data from SPD EEPROM dump")
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parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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@ -345,9 +346,8 @@ def main():
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soc_kwargs["sdram_module"] = args.sdram_module
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soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
|
||||
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
|
||||
if args.sdram_from_spd_data:
|
||||
with open(args.sdram_from_spd_data, "rb") as f:
|
||||
soc_kwargs["sdram_spd_data"] = [int(b) for b in f.read()]
|
||||
if args.sdram_from_spd_dump:
|
||||
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(args.sdram_from_spd_dump)
|
||||
|
||||
if args.with_ethernet or args.with_etherbone:
|
||||
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})
|
||||
|
|
|
|||
Loading…
Reference in New Issue