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cores/clock: add divclk_divide_range on S6PLL/S6DCM

This commit is contained in:
Florent Kermarrec 2019-04-23 06:43:48 +02:00
parent 0d282f38f9
commit 40342404f2
1 changed files with 2 additions and 0 deletions
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2
litex/soc/cores/clock.py
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@ -126,6 +126,7 @@ class S6PLL(XilinxClocking):
def __init__(self, speedgrade=-1): def __init__(self, speedgrade=-1):
XilinxClocking.__init__(self) XilinxClocking.__init__(self)
self.divclk_divide_range = (1, 52 + 1)
self.vco_freq_range = { self.vco_freq_range = {
-1: (400e6, 1000e6), -1: (400e6, 1000e6),
-2: (400e6, 1000e6), -2: (400e6, 1000e6),
@ -164,6 +165,7 @@ class S6DCM(XilinxClocking):
def __init__(self, speedgrade=-1): def __init__(self, speedgrade=-1):
XilinxClocking.__init__(self) XilinxClocking.__init__(self)
self.divclk_divide_range = (1, 1) # FIXME
self.clkin_freq_range = { self.clkin_freq_range = {
-1: (0.5e6, 200e6), -1: (0.5e6, 200e6),
-2: (0.5e6, 333e6), -2: (0.5e6, 333e6),