interconnect/axi/axi_full: Fix missing switch to LiteXModule.
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@ -602,12 +602,12 @@ def get_check_parameters(ports):
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return data_width
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class AXIInterconnectPointToPoint(Module):
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class AXIInterconnectPointToPoint(LiteXModule):
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"""AXI point to point interconnect"""
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def __init__(self, master, slave):
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self.comb += master.connect(slave)
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class AXIInterconnectShared(Module):
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class AXIInterconnectShared(LiteXModule):
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"""AXI shared interconnect"""
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def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
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data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
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