litescope: more pep8 (when convenient), should be almost OK

misoclib/tools/litescope/bridge/uart2wb.py

@@ -51,6 +51,7 @@ class LiteScopeUART2WB(Module, AutoCSR):
         "write": 0x01,
         "read": 0x02
     }
+
     def __init__(self, pads, clk_freq, baudrate=115200, share_uart=False):
         self.wishbone = wishbone.Interface()
         if share_uart:

misoclib/tools/litescope/core/storage.py

@@ -136,19 +136,25 @@ class LiteScopeRecorderUnit(Module):
             data_sink.ack.eq(fifo.sink.ack),
 
             fifo.source.ack.eq(fifo.fifo.level >= self.offset),
-            If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING"))
+            If(trigger_sink.stb & trigger_sink.hit,
+                NextState("POST_HIT_RECORDING")
+            )
         )
         fsm.act("POST_HIT_RECORDING",
             self.post_hit.eq(1),
             If(self.qualifier,
-                fifo.sink.stb.eq(trigger_sink.stb & trigger_sink.hit & data_sink.stb)
+                fifo.sink.stb.eq(trigger_sink.stb &
+                                 trigger_sink.hit &
+                                 data_sink.stb)
             ).Else(
                 fifo.sink.stb.eq(data_sink.stb)
             ),
             fifo.sink.data.eq(data_sink.data),
             data_sink.ack.eq(fifo.sink.ack),
 
-            If(~fifo.sink.ack | (fifo.fifo.level >= self.length), NextState("IDLE"))
+            If(~fifo.sink.ack | (fifo.fifo.level >= self.length),
+                NextState("IDLE")
+            )
         )
 
 

misoclib/tools/litescope/example_designs/targets/simple.py

@@ -15,6 +15,7 @@ class LiteScopeSoC(SoC, AutoCSR):
         "la":    17
     }
     csr_map.update(SoC.csr_map)
+
     def __init__(self, platform):
         clk_freq = int((1/(platform.default_clk_period))*1000000000)
         SoC.__init__(self, platform, clk_freq,

misoclib/tools/litescope/example_designs/test/test_io.py

@@ -17,13 +17,13 @@ def led_anim1(io):
         for i in range(8):
             io.write(led_data)
             time.sleep(i*i*0.0020)
-            led_data = (led_data<<1)
+            led_data = (led_data << 1)
         # Led >>
         ledData = 128
         for i in range(8):
             io.write(led_data)
             time.sleep(i*i*0.0020)
-            led_data = (led_data>>1)
+            led_data = (led_data >> 1)
 
 
 def main(wb):

misoclib/tools/litescope/frontend/la.py

@@ -48,7 +48,8 @@ class LiteScopeLA(Module, AutoCSR):
         # XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation
         if self.clk_domain is not "sys":
             self.submodules.fifo = AsyncFIFO(self.sink.description, 32)
-            self.submodules += RenameClockDomains(self.fifo, {"write": self.clk_domain, "read": "sys"})
+            self.submodules += RenameClockDomains(self.fifo,
+                {"write": self.clk_domain, "read": "sys"})
             self.comb += Record.connect(sink, self.fifo.sink)
             sink = self.fifo.source