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vexriscv: Add full and full_debug CPU variant

This commit is contained in:
Joanna Brozek 2019-04-12 17:23:23 +02:00 committed by Mateusz Hołenko
parent 017147c623
commit 40de01bcb0
2 changed files with 4 additions and 2 deletions
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4
litex/soc/cores/cpu/vexriscv/core.py
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@ -16,7 +16,7 @@ class VexRiscv(Module, AutoCSR):
def __init__(self, platform, cpu_reset_address, variant=None): def __init__(self, platform, cpu_reset_address, variant=None):
variant = "std" if variant is None else variant variant = "std" if variant is None else variant
variant = "std_debug" if variant == "debug" else variant variant = "std_debug" if variant == "debug" else variant
variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug") variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug", "full", "full_debug")
assert variant in variants, "Unsupported variant %s" % variant assert variant in variants, "Unsupported variant %s" % variant
self.platform = platform self.platform = platform
self.variant = variant self.variant = variant
@ -157,6 +157,8 @@ class VexRiscv(Module, AutoCSR):
"lite_debug": "VexRiscv_LiteDebug.v", "lite_debug": "VexRiscv_LiteDebug.v",
"min": "VexRiscv_Min.v", "min": "VexRiscv_Min.v",
"min_debug": "VexRiscv_MinDebug.v", "min_debug": "VexRiscv_MinDebug.v",
"full": "VexRiscv_Full.v",
"full_debug": "VexRiscv_FullDebug.v",
} }
cpu_filename = verilog_variants[variant] cpu_filename = verilog_variants[variant]
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog") vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")

2
litex/soc/cores/cpu/vexriscv/verilog

@ -1 +1 @@
Subproject commit d7bbc2c167f1a0886c446d3c305d0ed4388570be Subproject commit ebe4064653bc143bf92a0ccdd1099173620fcbf5