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utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified

This commit is contained in:
Florent Kermarrec 2019-03-13 10:42:10 +01:00
parent 7ec3ed4d89
commit 411bca790a
1 changed files with 4 additions and 2 deletions
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6
litex/utils/litex_sim.py
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@ -218,11 +218,11 @@ def main():
if args.rom_init: if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init) soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
if not args.with_sdram: if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000 soc_kwargs["integrated_main_ram_size"] = 0x1000000 # 256 MB
if args.ram_init is not None: if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init) soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init)
soc_kwargs["integrated_main_ram_size"] = max(len(soc_kwargs["integrated_main_ram_init"]), 0x10000)
else: else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0 soc_kwargs["integrated_main_ram_size"] = 0x0
if args.with_ethernet: if args.with_ethernet:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"}) sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
@ -235,6 +235,8 @@ def main():
with_etherbone=args.with_etherbone, with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer, with_analyzer=args.with_analyzer,
**soc_kwargs) **soc_kwargs)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
builder_kwargs["csr_csv"] = "csr.csv" builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs) builder = Builder(soc, **builder_kwargs)
vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, trace=args.trace) vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, trace=args.trace)