xilinx/vivado: Fix issue with #1755.
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@ -170,9 +170,8 @@ class XilinxVivadoToolchain(GenericToolchain):
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True : "ports",
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}[hasattr(clk, "port")]
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for clk, [period, name] in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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clk_sig = self._vns.get_name(clk)
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if name is None:
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name = clk_sig
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name = clk
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self.platform.add_platform_command(
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"create_clock -name {name} -period " + str(period) +
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" [get_" + get_clk_type(clk) + " {clk}]", name=name, clk=clk)
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