Update CV32E40P to be based on the OpenHW Group's repo
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Nuntipat Narkthong
parent
2613ae606a
commit
41564cc47b
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@ -19,7 +19,7 @@ from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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# Variants -----------------------------------------------------------------------------------------
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CPU_VARIANTS = ["standard", "full"]
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CPU_VARIANTS = ["standard", "standard+fpu"]
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# GCC Flags ----------------------------------------------------------------------------------------
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@ -32,7 +32,7 @@ GCC_FLAGS = {
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# | ||||/-- Double-Precision Floating-Point
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# i macfd
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"standard": "-march=rv32i2p0_mc -mabi=ilp32 ",
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"full": "-march=rv32i2p0_mfc -mabi=ilp32 ",
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"standard+fpu": "-march=rv32i2p0_mfc -mabi=ilp32 ",
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}
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# OBI / APB / Trace Layouts ------------------------------------------------------------------------
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@ -59,18 +59,6 @@ apb_layout = [
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("pslverr", 1),
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]
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trace_layout = [
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("ivalid", 1),
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("iexception", 1),
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("interrupt", 1),
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("cause", 5),
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("tval", 32),
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("priv", 3),
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("iaddr", 32),
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("instr", 32),
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("compressed", 1),
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]
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# Helpers ------------------------------------------------------------------------------------------
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def add_manifest_sources(platform, manifest):
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@ -182,102 +170,6 @@ class Wishbone2APB(LiteXModule):
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wb.dat_r.eq(apb.prdata),
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]
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# Trace Collector ----------------------------------------------------------------------------------
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class TraceCollector(LiteXModule):
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def __init__(self, trace_depth=16384):
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self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.sink = sink = stream.Endpoint([("data", 32)])
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clear = Signal()
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enable = Signal()
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pointer = Signal(32)
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self._enable = CSRStorage()
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self._clear = CSRStorage()
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self._pointer = CSRStatus(32)
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mem = Memory(32, trace_depth)
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rd_port = mem.get_port()
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wr_port = mem.get_port(write_capable=True)
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self.specials += rd_port, wr_port, mem
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self.sync += [
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# wishbone
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bus.ack.eq(0),
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If(bus.cyc & bus.stb & ~bus.ack, bus.ack.eq(1)),
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# trace core
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If(clear, pointer.eq(0)).Else(
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If(sink.ready & sink.valid, pointer.eq(pointer+1)),
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),
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]
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self.comb += [
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# wishbone
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rd_port.adr.eq(bus.adr),
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bus.dat_r.eq(rd_port.dat_r),
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# trace core
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wr_port.adr.eq(pointer),
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wr_port.dat_w.eq(sink.data),
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wr_port.we.eq(sink.ready & sink.valid),
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sink.ready.eq(enable & (pointer < trace_depth)),
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# csrs
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enable.eq(self._enable.storage),
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clear.eq(self._clear.storage),
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self._pointer.status.eq(pointer),
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]
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# Trace Debugger -----------------------------------------------------------------------------------
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class TraceDebugger(LiteXModule):
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def __init__(self):
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self.bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.source = source = stream.Endpoint([("data", 32)])
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self.trace_if = trace_if = Record(trace_layout)
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apb = Record(apb_layout)
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self.bus_conv = Wishbone2APB(self.bus, apb)
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self.trace_params = dict(
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# Clk / Rst.
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i_clk_i = ClockSignal("sys"),
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i_rst_ni = ~ResetSignal("sys"),
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i_test_mode_i = 0,
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# CPU Interface.
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i_ivalid_i = trace_if.ivalid,
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i_iexception_i = trace_if.iexception,
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i_interrupt_i = trace_if.interrupt,
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i_cause_i = trace_if.cause,
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i_tval_i = trace_if.tval,
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i_priv_i = trace_if.priv,
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i_iaddr_i = trace_if.iaddr,
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i_instr_i = trace_if.instr,
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i_compressed_i = trace_if.compressed,
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# APB Interface.
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i_paddr_i = apb.paddr,
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i_pwdata_i = apb.pwdata,
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i_pwrite_i = apb.pwrite,
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i_psel_i = apb.psel,
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i_penable_i = apb.penable,
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o_prdata_o = apb.prdata,
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o_pready_o = apb.pready,
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o_pslverr_o = apb.pslverr,
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# Data Output.
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o_packet_word_o = source.data,
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o_packet_word_valid_o = source.valid,
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i_grant_i = source.ready,
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)
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self.specials += Instance("trace_debugger", **self.trace_params)
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@staticmethod
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def add_sources(platform):
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add_manifest_sources(platform, "cv32e40p_trace_manifest.flist")
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# Debug Module -------------------------------------------------------------------------------------
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class DebugModule(LiteXModule):
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@ -350,10 +242,6 @@ class DebugModule(LiteXModule):
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self.specials += Instance("dm_wrap", **self.dm_params)
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@staticmethod
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def add_sources(platform):
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add_manifest_sources(platform, "cv32e40p_dm_manifest.flist")
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# CV32E40P -----------------------------------------------------------------------------------------
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class CV32E40P(CPU):
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@ -368,8 +256,7 @@ class CV32E40P(CPU):
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linker_output_format = "elf32-littleriscv"
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nop = "nop"
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io_regions = {0x80000000: 0x80000000} # Origin, Length.
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has_fpu = ["full"]
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has_fpu = ["standard+fpu"]
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# GCC Flags.
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@property
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@ -379,14 +266,15 @@ class CV32E40P(CPU):
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return flags
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def __init__(self, platform, variant="standard"):
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.ibus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.dbus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.periph_buses = [self.ibus, self.dbus]
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self.memory_buses = []
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self.interrupt = Signal(15)
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.ibus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.dbus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.periph_buses = [self.ibus, self.dbus]
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self.memory_buses = []
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self.interrupt = Signal(16)
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self.interrupt_padding = Signal(16)
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ibus = Record(obi_layout)
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dbus = Record(obi_layout)
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@ -406,11 +294,12 @@ class CV32E40P(CPU):
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i_rst_ni = ~ResetSignal("sys"),
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# Controls.
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i_clock_en_i = 1,
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i_test_en_i = 0,
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i_fregfile_disable_i = 0,
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i_core_id_i = 0,
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i_cluster_id_i = 0,
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i_pulp_clock_en_i = 1,
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i_scan_cg_en_i = 0,
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i_mtvec_addr_i = 0,
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i_dm_halt_addr_i = 0,
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i_hart_id_i = 0,
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i_dm_exception_addr_i = 0,
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# IBus.
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o_instr_req_o = ibus.req,
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@ -429,56 +318,32 @@ class CV32E40P(CPU):
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o_data_wdata_o = dbus.wdata,
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i_data_rdata_i = dbus.rdata,
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# APU.
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i_apu_master_gnt_i = 0,
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i_apu_master_valid_i = 0,
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# IRQ.
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i_irq_sec_i = 0,
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i_irq_software_i = 0,
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i_irq_external_i = 0,
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i_irq_fast_i = self.interrupt,
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i_irq_nmi_i = 0,
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i_irq_fastx_i = 0,
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i_irq_i = Cat(self.interrupt_padding, self.interrupt),
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# Debug.
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i_debug_req_i = 0,
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i_debug_req_i = 0,
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# CPU Control.
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i_fetch_enable_i = 1,
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i_fetch_enable_i = 1,
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)
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# Add Verilog sources.
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add_manifest_sources(platform, 'cv32e40p_manifest.flist')
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# Specific FPU variant parameters/files.
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if variant in self.has_fpu:
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# Specific FPU variant parameters/files.
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self.cpu_params.update(p_FPU=1)
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add_manifest_sources(platform, 'cv32e40p_fpu_manifest.flist')
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else:
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add_manifest_sources(platform, 'cv32e40p_manifest.flist')
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def add_debug_module(self, dm):
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self.cpu_params.update(i_debug_req_i=dm.debug_req)
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self.cpu_params.update(i_rst_ni=~(ResetSignal("sys") | dm.ndmreset))
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def add_trace_core(self, trace):
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trace_if = trace.trace_if
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self.cpu_params.update(
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o_ivalid_o = trace_if.ivalid,
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o_iexception_o = trace_if.iexception,
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o_interrupt_o = trace_if.interrupt,
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o_cause_o = trace_if.cause,
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o_tval_o = trace_if.tval,
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o_priv_o = trace_if.priv,
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o_iaddr_o = trace_if.iaddr,
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o_instr_o = trace_if.instr,
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o_compressed_o = trace_if.compressed,
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)
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def set_reset_address(self, reset_address):
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self.reset_address = reset_address
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self.cpu_params.update(i_boot_addr_i=Signal(32, reset=reset_address))
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("riscv_core", **self.cpu_params)
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self.specials += Instance("cv32e40p_core", **self.cpu_params)
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@ -46,7 +46,7 @@ vector_table:
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j trap_entry # 28 firq12
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j trap_entry # 29 firq13
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j trap_entry # 30 firq14
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j trap_entry # 31 unused
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j trap_entry # 31 firq15
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.global trap_entry
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trap_entry:
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@ -116,10 +116,8 @@ bss_loop:
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add a0,a0,4
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j bss_loop
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bss_done:
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li a0, 0x7FFF0880 //7FFF0880 enable timer + external interrupt + fast interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
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li a0, 0xFFFF0880 //FFFF0880 enable timer + external interrupt + fast interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
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csrw mie,a0
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j main
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infinit_loop:
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j infinit_loop
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@ -1,11 +1,14 @@
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#ifndef CSR_DEFS__H
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#define CSR_DEFS__H
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/*Reference : https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/control_status_registers.html */
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#define CSR_MSTATUS_MIE 0x8
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#define CSR_IRQ_MASK 0xBC0
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#define CSR_IRQ_PENDING 0xFC0
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#define CSR_IRQ_MASK 0x304
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#define CSR_IRQ_PENDING 0x344
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#define FIRQ_OFFSET 16
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#define CSR_DCACHE_INFO 0xCC0
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#endif /* CSR_DEFS__H */
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@ -20,17 +20,21 @@ static inline void irq_setie(unsigned int ie)
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static inline unsigned int irq_getmask(void)
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{
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return 0; // FIXME
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unsigned int mask;
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asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
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return (mask >> FIRQ_OFFSET);
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}
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static inline void irq_setmask(unsigned int mask)
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{
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// FIXME
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asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask << FIRQ_OFFSET));
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}
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static inline unsigned int irq_pending(void)
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{
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return 0;// FIXME
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unsigned int pending;
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asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
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return (pending >> FIRQ_OFFSET);
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}
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#ifdef __cplusplus
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@ -7,17 +7,8 @@
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extern "C" {
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#endif
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__attribute__((unused)) static void flush_cpu_icache(void)
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{
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// FIXME
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asm volatile("nop");
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}
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__attribute__((unused)) static void flush_cpu_dcache(void)
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{
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// FIXME
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asm volatile("nop");
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}
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__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */
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__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */
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void flush_l2_cache(void);
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