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minicon: small simplifications

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This commit is contained in:
Sebastien Bourdeauducq 2014-11-28 08:28:39 +08:00
parent edb1622668
commit 4189440eef
1 changed files with 11 additions and 18 deletions
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23
misoclib/sdram/minicon/__init__.py
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@ -57,7 +57,6 @@ class Minicon(Module):
slicer = _AddressSlicer(geom_settings.col_a, geom_settings.bank_a, geom_settings.row_a, address_align) slicer = _AddressSlicer(geom_settings.col_a, geom_settings.bank_a, geom_settings.row_a, address_align)
refresh_req = Signal() refresh_req = Signal()
refresh_ack = Signal() refresh_ack = Signal()
wb_access = Signal()
refresh_counter = Signal(max=timing_settings.tREFI+1) refresh_counter = Signal(max=timing_settings.tREFI+1)
hit = Signal() hit = Signal()
row_open = Signal() row_open = Signal()
@ -71,24 +70,18 @@ class Minicon(Module):
self.comb += [ self.comb += [
hit.eq(openrow[slicer.bank(bus.adr)] == Cat(slicer.row(bus.adr), 1)), hit.eq(openrow[slicer.bank(bus.adr)] == Cat(slicer.row(bus.adr), 1)),
has_curbank_openrow.eq(openrow[slicer.bank(bus.adr)][-1]), has_curbank_openrow.eq(openrow[slicer.bank(bus.adr)][-1]),
wb_access.eq(bus.stb & bus.cyc), bus.dat_r.eq(Cat(phase.rddata for phase in dfi.phases)),
bus.dat_r.eq(Cat([phase.rddata for phase in dfi.phases])), Cat(phase.wrdata for phase in dfi.phases).eq(bus.dat_w),
Cat([phase.wrdata for phase in dfi.phases]).eq(bus.dat_w), Cat(phase.wrdata_mask for phase in dfi.phases).eq(~bus.sel),
Cat([phase.wrdata_mask for phase in dfi.phases]).eq(~bus.sel),
] ]
for phase in dfi.phases: for phase in dfi.phases:
self.comb += [ self.comb += [
phase.cke.eq(1), phase.cke.eq(1),
phase.cs_n.eq(0),
phase.address.eq(Array([2**10, slicer.col(bus.adr), slicer.row(bus.adr)])[addr_sel]), phase.address.eq(Array([2**10, slicer.col(bus.adr), slicer.row(bus.adr)])[addr_sel]),
If(wb_access,
phase.bank.eq(slicer.bank(bus.adr)) phase.bank.eq(slicer.bank(bus.adr))
)
] ]
phase.cs_n.reset = 0
phase.ras_n.reset = 1
phase.cas_n.reset = 1
phase.we_n.reset = 1
for b in nbanks: for b in nbanks:
self.sync += [ self.sync += [
@ -117,12 +110,12 @@ class Minicon(Module):
fsm.act("IDLE", fsm.act("IDLE",
If(refresh_req, If(refresh_req,
NextState("PRECHARGEALL") NextState("PRECHARGEALL")
).Elif(wb_access, ).Elif(bus.stb & bus.cyc,
If(hit & bus.we, If(hit & bus.we,
NextState("WRITE"), NextState("WRITE")
), ),
If(hit & ~bus.we, If(hit & ~bus.we,
NextState("READ"), NextState("READ")
), ),
If(has_curbank_openrow & ~hit, If(has_curbank_openrow & ~hit,
NextState("PRECHARGE") NextState("PRECHARGE")
@ -133,7 +126,7 @@ class Minicon(Module):
) )
) )
fsm.act("READ", fsm.act("READ",
# We output Column bits at address pins so that A10 is 0 # We output Column bits at address pins so A10 is 0
# to disable row Auto-Precharge # to disable row Auto-Precharge
dfi.phases[rdphase].ras_n.eq(1), dfi.phases[rdphase].ras_n.eq(1),
dfi.phases[rdphase].cas_n.eq(0), dfi.phases[rdphase].cas_n.eq(0),