Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/cores/icap: simplify ICAPBitstream (untested)

This commit is contained in:
Florent Kermarrec 2019-10-01 21:30:14 +02:00
parent 0c2993866c
commit 41ad08e8ef
2 changed files with 41 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

75
litex/soc/cores/icap.py
View File

@ -25,7 +25,7 @@ class ICAP(Module, AutoCSR):
# # # # # #
# Create slow icap clk (sys_clk/2) --------------------------------------------------------- # Create slow icap clk (sys_clk/16) ---------------------------------------------------------
self.clock_domains.cd_icap = ClockDomain() self.clock_domains.cd_icap = ClockDomain()
icap_clk_counter = Signal(4) icap_clk_counter = Signal(4)
self.sync += icap_clk_counter.eq(icap_clk_counter + 1) self.sync += icap_clk_counter.eq(icap_clk_counter + 1)
@ -36,7 +36,7 @@ class ICAP(Module, AutoCSR):
self.submodules += ps_send self.submodules += ps_send
self.comb += [ps_send.i.eq(self.send.re)] self.comb += [ps_send.i.eq(self.send.re)]
# generate icap bitstream write sequence # Generate icap bitstream write sequenceenerate icap bitstream write sequence
_csib = Signal(reset=1) _csib = Signal(reset=1)
_i = Signal(32) _i = Signal(32)
_addr = self.addr.storage << 13 _addr = self.addr.storage << 13
@ -62,9 +62,9 @@ class ICAP(Module, AutoCSR):
] ]
self._csib = _csib self._csib = _csib
self._i = _i self._i = _i
# icap instance # ICAP instance
if not simulation: if not simulation:
self.specials += [ self.specials += [
Instance("ICAPE2", Instance("ICAPE2",
@ -76,64 +76,61 @@ class ICAP(Module, AutoCSR):
) )
] ]
class ICAPBitstream(Module, AutoCSR): class ICAPBitstream(Module, AutoCSR):
"""ICAP """ICAP
Allow sending bitstreams to ICAPE2 of Xilinx 7-Series FPGAs. Allow sending bitstreams to ICAPE2 of Xilinx 7-Series FPGAs.
""" """
def __init__(self, simulation=False): def __init__(self, fifo_depth=8, simulation=False):
self.data = CSRStorage(32, reset=0xffffffff) self.sink_data = CSRStorage(32)
self.icap_en = CSRStorage(reset=0) self.sink_ready = CSRStatus()
self.fifofull = CSRStatus() self.start = CSR()
self.done = CSRStatus(reset=1) self.done = CSRStatus()
# # # # # #
_run = Signal()
_csib = Signal(reset=1)
_i = Signal(32, reset=0xffffffff)
# Create slow icap clk (sys_clk/4) --------------------------------------------------------- # Create slow icap clk (sys_clk/4) ---------------------------------------------------------
self.clock_domains.cd_icap = ClockDomain() self.clock_domains.cd_icap = ClockDomain()
icap_clk_counter = Signal(4) icap_clk_counter = Signal(4)
self.sync += icap_clk_counter.eq(icap_clk_counter + 1) self.sync += icap_clk_counter.eq(icap_clk_counter + 1)
self.sync += self.cd_icap.clk.eq(icap_clk_counter[1]) self.sync += self.cd_icap.clk.eq(icap_clk_counter[1])
# Helper signals
_csib = Signal(reset=1)
_i = Signal(32, reset=0xffffffff)
acknext = Signal(reset=0)
syncdata = Signal(32, reset=0xffffffff)
# FIFO # FIFO
fifo = stream.AsyncFIFO([("data", 32)], 8) fifo = stream.AsyncFIFO([("data", 32)], fifo_depth)
icapfifo = ClockDomainsRenamer({"write": "sys", "read": "icap"})(fifo) fifo = ClockDomainsRenamer({"write": "sys", "read": "icap"})(fifo)
self.submodules += fifo
# Connect to FIFO
self.comb += [ self.comb += [
icapfifo.sink.valid.eq(self.data.re), fifo.sink.valid.eq(self.sink_data.re),
icapfifo.sink.data.eq(self.data.storage), fifo.sink.data.eq(self.sink_data.storage),
self.fifofull.status.eq(~icapfifo.sink.ready), self.sink_ready.status.eq(fifo.sink.ready),
syncdata.eq(icapfifo.source.data),
icapfifo.source.ready.eq(acknext),
] ]
self.submodules += icapfifo
# Generate ICAP commands
self.sync.icap += [ self.sync.icap += [
If(self.icap_en.storage & icapfifo.source.valid & ~acknext, If(self.start.re,
acknext.eq(1), _run.eq(1),
self.done.status.eq(0) ).Elif(~fifo.source.valid,
).Elif(self.icap_en.storage & icapfifo.source.valid & acknext, _run.eq(0)
_i.eq(syncdata), )
_csib.eq(0) ]
).Else( self.comb += [
_i.eq(0xffffffff), self.done.status.eq(~_run),
_csib.eq(1), If(_run,
acknext.eq(0), _i.eq(fifo.source.data),
self.done.status.eq(1) _csib.eq(0),
), fifo.source.ready.eq(1)
)
] ]
self._csib = _csib self._csib = _csib
self._i = _i self._i = _i
# icap instance # ICAP instance
if not simulation: if not simulation:
self.specials += [ self.specials += [
Instance("ICAPE2", Instance("ICAPE2",

7
test/test_icap.py
View File

@ -5,11 +5,11 @@ import unittest
from migen import * from migen import *
from litex.soc.cores.icap import ICAP from litex.soc.cores.icap import ICAP, ICAPBitstream
class TestICAP(unittest.TestCase): class TestICAP(unittest.TestCase):
def test_reload(self): def test_icap_command_reload(self):
def generator(dut): def generator(dut):
yield dut.addr.storage.eq(0x4) yield dut.addr.storage.eq(0x4)
yield dut.data.storage.eq(0xf) yield dut.data.storage.eq(0xf)
@ -25,3 +25,6 @@ class TestICAP(unittest.TestCase):
clocks = {"sys": 10, clocks = {"sys": 10,
"icap":20} "icap":20}
run_simulation(dut, generator(dut), clocks, vcd_name="icap.vcd") run_simulation(dut, generator(dut), clocks, vcd_name="icap.vcd")
def test_icap_bitstream_syntax(self):
dut = ICAPBitstream(simulation=True)