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targets/kc705: integrate DDR3

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This commit is contained in:
Sebastien Bourdeauducq 2014-08-08 21:58:41 +08:00
parent 0ebdf2be6d
commit 41c8c172b5
1 changed files with 25 additions and 8 deletions
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33
targets/kc705.py
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@ -1,8 +1,9 @@
from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.bus import wishbone
from misoclib.gensoc import GenSoC, IntegratedBIOS
from misoclib import lasmicon
from misoclib.sdramphy import k7ddrphy
from misoclib.gensoc import SDRAMSoC, IntegratedBIOS
class _CRG(Module):
def __init__(self, platform):
@ -58,19 +59,35 @@ class _CRG(Module):
)
self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
class BaseSoC(GenSoC, IntegratedBIOS):
class BaseSoC(SDRAMSoC, IntegratedBIOS):
default_platform = "kc705"
def __init__(self, platform, **kwargs):
GenSoC.__init__(self, platform,
SDRAMSoC.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0,
**kwargs)
IntegratedBIOS.__init__(self)
sdram_geom = lasmicon.GeomSettings(
bank_a=3,
row_a=16,
col_a=10
)
sdram_timing = lasmicon.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(15),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
self.submodules.crg = _CRG(platform)
self.submodules.usermem = wishbone.SRAM(64*1024)
self.add_wb_slave(lambda a: a[27:29] == 2, self.usermem.bus)
self.add_cpu_memory_region("sdram", 0x40000000, 64*1024)
default_subtarget = BaseSoC