build/sim/verilator: fixed missing placeholder

2022-08-04 20:03:29 +01:00 · 2022-08-04 20:03:29 +01:00 · 41e1ccce4b
parent 926fb9a30a
commit 41e1ccce4b
1 changed files with 1 additions and 1 deletions
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@ -137,7 +137,7 @@ def _build_sim(build_name, sources, jobs, threads, coverage, opt_level="O3", tra
        cc_srcs.append("--cc " + filename + " ")
    build_script_contents = """\
 rm -rf obj_dir/
-make -C . -f {} {} {} {} {} {}
+make -C . -f {} {} {} {} {} {} {}
 """.format(makefile,
    "CC_SRCS=\"{}\"".format("".join(cc_srcs)),
    "JOBS={}".format(jobs) if jobs else "",