soc/cores/cpu/naxriscv/core: fix arch definition
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@ -69,7 +69,7 @@ class NaxRiscv(CPU):
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# Arch.
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@staticmethod
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def get_arch():
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arch = f"rv{NaxRiscv.xlen}ima"
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arch = f"rv{NaxRiscv.xlen}i2p0_ma"
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if NaxRiscv.with_fpu:
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arch += "fd"
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if NaxRiscv.with_rvc:
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