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lasmi: reduce latencies by 1 cycle

This commit is contained in:
Sebastien Bourdeauducq 2013-06-11 15:26:47 +02:00
parent 91d7b656a9
commit 422c9a1db9
4 changed files with 24 additions and 63 deletions
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8
milkymist/dfii/__init__.py
View File

@ -13,7 +13,6 @@ class PhaseInjector(Module, AutoCSR):
### ###
wrdata_en_adv = Signal()
self.comb += [ self.comb += [
If(self._command_issue.re, If(self._command_issue.re,
phase.cs_n.eq(~self._command.storage[0]), phase.cs_n.eq(~self._command.storage[0]),
@ -28,15 +27,12 @@ class PhaseInjector(Module, AutoCSR):
), ),
phase.address.eq(self._address.storage), phase.address.eq(self._address.storage),
phase.bank.eq(self._baddress.storage), phase.bank.eq(self._baddress.storage),
wrdata_en_adv.eq(self._command_issue.re & self._command.storage[4]), phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]), phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
phase.wrdata.eq(self._wrdata.storage), phase.wrdata.eq(self._wrdata.storage),
phase.wrdata_mask.eq(0) phase.wrdata_mask.eq(0)
] ]
self.sync += [ self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
phase.wrdata_en.eq(wrdata_en_adv),
If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
]
class DFIInjector(Module, AutoCSR): class DFIInjector(Module, AutoCSR):
def __init__(self, a, ba, d, nphases=1): def __init__(self, a, ba, d, nphases=1):

4
milkymist/lasmicon/multiplexer.py
View File

@ -65,7 +65,6 @@ class _Steerer(Module):
else: else:
return cmd.stb & getattr(cmd, attr) return cmd.stb & getattr(cmd, attr)
for phase, sel in zip(dfi.phases, self.sel): for phase, sel in zip(dfi.phases, self.sel):
wrdata_en_adv = Signal()
self.comb += [ self.comb += [
phase.cke.eq(1), phase.cke.eq(1),
phase.cs_n.eq(0) phase.cs_n.eq(0)
@ -77,8 +76,7 @@ class _Steerer(Module):
phase.ras_n.eq(Array(cmd.ras_n for cmd in commands)[sel]), phase.ras_n.eq(Array(cmd.ras_n for cmd in commands)[sel]),
phase.we_n.eq(Array(cmd.we_n for cmd in commands)[sel]), phase.we_n.eq(Array(cmd.we_n for cmd in commands)[sel]),
phase.rddata_en.eq(Array(stb_and(cmd, "is_read") for cmd in commands)[sel]), phase.rddata_en.eq(Array(stb_and(cmd, "is_read") for cmd in commands)[sel]),
wrdata_en_adv.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel]), phase.wrdata_en.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel])
phase.wrdata_en.eq(wrdata_en_adv)
] ]
class Multiplexer(Module): class Multiplexer(Module):

4
top.py
View File

@ -44,8 +44,8 @@ sdram_timing = lasmicon.TimingSettings(
tRFC=ns(70), tRFC=ns(70),
CL=3, CL=3,
read_latency=5, read_latency=4,
write_latency=1, write_latency=0,
read_time=32, read_time=32,
write_time=16 write_time=16

71
verilog/s6ddrphy/s6ddrphy.v
View File

@ -2,12 +2,12 @@
* 1:2 frequency-ratio DDR PHY for Spartan-6 * 1:2 frequency-ratio DDR PHY for Spartan-6
* *
* Assert dfi_wrdata_en and present the data * Assert dfi_wrdata_en and present the data
* on dfi_wrdata_mask/dfi_wrdata in the cycle * on dfi_wrdata_mask/dfi_wrdata in the same
* immediately following the write command. * cycle as the write command.
* *
* Assert dfi_rddata_en in the same cycle as the read * Assert dfi_rddata_en in the same cycle as the read
* command. The data will come back on dfi_rddata * command. The data will come back on dfi_rddata
* 5 cycles later, along with the assertion of * 4 cycles later, along with the assertion of
* dfi_rddata_valid. * dfi_rddata_valid.
* *
* This PHY only supports CAS Latency 3. * This PHY only supports CAS Latency 3.
@ -75,39 +75,6 @@ module s6ddrphy #(
* Command/address * Command/address
*/ */
reg [NUM_AD-1:0] r0_dfi_address_p0;
reg [NUM_BA-1:0] r0_dfi_bank_p0;
reg r0_dfi_cs_n_p0;
reg r0_dfi_cke_p0;
reg r0_dfi_ras_n_p0;
reg r0_dfi_cas_n_p0;
reg r0_dfi_we_n_p0;
reg [NUM_AD-1:0] r0_dfi_address_p1;
reg [NUM_BA-1:0] r0_dfi_bank_p1;
reg r0_dfi_cs_n_p1;
reg r0_dfi_cke_p1;
reg r0_dfi_ras_n_p1;
reg r0_dfi_cas_n_p1;
reg r0_dfi_we_n_p1;
always @(posedge sys_clk) begin
r0_dfi_address_p0 <= dfi_address_p0;
r0_dfi_bank_p0 <= dfi_bank_p0;
r0_dfi_cs_n_p0 <= dfi_cs_n_p0;
r0_dfi_cke_p0 <= dfi_cke_p0;
r0_dfi_ras_n_p0 <= dfi_ras_n_p0;
r0_dfi_cas_n_p0 <= dfi_cas_n_p0;
r0_dfi_we_n_p0 <= dfi_we_n_p0;
r0_dfi_address_p1 <= dfi_address_p1;
r0_dfi_bank_p1 <= dfi_bank_p1;
r0_dfi_cs_n_p1 <= dfi_cs_n_p1;
r0_dfi_cke_p1 <= dfi_cke_p1;
r0_dfi_ras_n_p1 <= dfi_ras_n_p1;
r0_dfi_cas_n_p1 <= dfi_cas_n_p1;
r0_dfi_we_n_p1 <= dfi_we_n_p1;
end
reg phase_sel; reg phase_sel;
always @(posedge clk2x_270) always @(posedge clk2x_270)
phase_sel <= sys_clk; phase_sel <= sys_clk;
@ -128,21 +95,21 @@ reg r_dfi_cas_n_p1;
reg r_dfi_we_n_p1; reg r_dfi_we_n_p1;
always @(posedge clk2x_270) begin always @(posedge clk2x_270) begin
r_dfi_address_p0 <= r0_dfi_address_p0; r_dfi_address_p0 <= dfi_address_p0;
r_dfi_bank_p0 <= r0_dfi_bank_p0; r_dfi_bank_p0 <= dfi_bank_p0;
r_dfi_cs_n_p0 <= r0_dfi_cs_n_p0; r_dfi_cs_n_p0 <= dfi_cs_n_p0;
r_dfi_cke_p0 <= r0_dfi_cke_p0; r_dfi_cke_p0 <= dfi_cke_p0;
r_dfi_ras_n_p0 <= r0_dfi_ras_n_p0; r_dfi_ras_n_p0 <= dfi_ras_n_p0;
r_dfi_cas_n_p0 <= r0_dfi_cas_n_p0; r_dfi_cas_n_p0 <= dfi_cas_n_p0;
r_dfi_we_n_p0 <= r0_dfi_we_n_p0; r_dfi_we_n_p0 <= dfi_we_n_p0;
r_dfi_address_p1 <= r0_dfi_address_p1; r_dfi_address_p1 <= dfi_address_p1;
r_dfi_bank_p1 <= r0_dfi_bank_p1; r_dfi_bank_p1 <= dfi_bank_p1;
r_dfi_cs_n_p1 <= r0_dfi_cs_n_p1; r_dfi_cs_n_p1 <= dfi_cs_n_p1;
r_dfi_cke_p1 <= r0_dfi_cke_p1; r_dfi_cke_p1 <= dfi_cke_p1;
r_dfi_ras_n_p1 <= r0_dfi_ras_n_p1; r_dfi_ras_n_p1 <= dfi_ras_n_p1;
r_dfi_cas_n_p1 <= r0_dfi_cas_n_p1; r_dfi_cas_n_p1 <= dfi_cas_n_p1;
r_dfi_we_n_p1 <= r0_dfi_we_n_p1; r_dfi_we_n_p1 <= dfi_we_n_p1;
end end
always @(posedge clk2x_270) begin always @(posedge clk2x_270) begin
@ -367,10 +334,10 @@ end
assign drive_dqs = r2_dfi_wrdata_en; assign drive_dqs = r2_dfi_wrdata_en;
wire rddata_valid; wire rddata_valid;
reg [5:0] rddata_sr; reg [4:0] rddata_sr;
assign dfi_rddata_valid_w0 = rddata_sr[0]; assign dfi_rddata_valid_w0 = rddata_sr[0];
assign dfi_rddata_valid_w1 = rddata_sr[0]; assign dfi_rddata_valid_w1 = rddata_sr[0];
always @(posedge sys_clk) always @(posedge sys_clk)
rddata_sr <= {dfi_rddata_en_p0, rddata_sr[5:1]}; rddata_sr <= {dfi_rddata_en_p0, rddata_sr[4:1]};
endmodule endmodule