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another minor change - reveal STARTUPE2 block's ring oscillator

This commit is contained in:
bunnie 2020-12-13 01:49:43 +08:00
parent 8ee0fdbf8e
commit 422cc2baae
1 changed files with 2 additions and 0 deletions
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2
litex/soc/cores/spi_opi.py
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@ -28,6 +28,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
self.cipo_name = cipo_name self.cipo_name = cipo_name
self.spiread = spiread self.spiread = spiread
self.gsr = Signal() self.gsr = Signal()
self.cfgmclk = Signal()
self.dq = dq = TSTriple(7) # dq[0] is special because it is also copi self.dq = dq = TSTriple(7) # dq[0] is special because it is also copi
self.dq_copi = dq_copi = TSTriple(1) # this has similar structure but an independent "oe" signal self.dq_copi = dq_copi = TSTriple(1) # this has similar structure but an independent "oe" signal
@ -298,6 +299,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
i_USRDONETS = 1, i_USRDONETS = 1,
i_USRCCLKO = 0, i_USRCCLKO = 0,
i_USRCCLKTS = 1, # Force to tristate i_USRCCLKTS = 1, # Force to tristate
o_CFGMCLK = self.cfgmclk,
), ),
Instance("ODDR", name=sclk_name, # Need to name this so we can constrain it properly Instance("ODDR", name=sclk_name, # Need to name this so we can constrain it properly
p_DDR_CLK_EDGE = "SAME_EDGE", p_DDR_CLK_EDGE = "SAME_EDGE",