integration/soc/add_scard: Revert use of self.csr.add since to avoid breaking Linux driver that currently relies on implicit ordering (but probably shoudln't :)).
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@ -1497,6 +1497,8 @@ class LiteXSoC(SoC):
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# Add SDCard -----------------------------------------------------------------------------------
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def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False, software_debug=False):
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# FIXME: Make sure Linux Driver does not rely on CSR implicit ordering and remove self.csr.add().
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# Imports.
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from litesdcard.emulator import SDEmulator
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from litesdcard.phy import SDPHY
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@ -1519,6 +1521,8 @@ class LiteXSoC(SoC):
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self.check_if_exists("sdcore")
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self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq, cmd_timeout=10e-1, data_timeout=10e-1)
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self.submodules.sdcore = SDCore(self.sdphy)
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self.csr.add("sdphy", use_loc_if_exists=True)
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self.csr.add("sdcore", use_loc_if_exists=True)
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# Block2Mem DMA.
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if "read" in mode:
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@ -1527,6 +1531,7 @@ class LiteXSoC(SoC):
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self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
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dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
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dma_bus.add_master("sdblock2mem", master=bus)
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self.csr.add("sdblock2mem", use_loc_if_exists=True)
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# Mem2Block DMA.
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if "write" in mode:
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@ -1535,6 +1540,7 @@ class LiteXSoC(SoC):
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self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
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dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
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dma_bus.add_master("sdmem2block", master=bus)
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self.csr.add("sdmem2block", use_loc_if_exists=True)
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# Interrupts.
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self.submodules.sdirq = EventManager()
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@ -1542,6 +1548,7 @@ class LiteXSoC(SoC):
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self.sdirq.block2mem_dma = EventSourcePulse(description="Block2Mem DMA terminated.")
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self.sdirq.mem2block_dma = EventSourcePulse(description="Mem2Block DMA terminated.")
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self.sdirq.finalize()
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self.csr.add("sdirq")
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self.comb += [
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self.sdirq.card_detect.trigger.eq(self.sdphy.card_detect_irq),
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self.sdirq.block2mem_dma.trigger.eq(self.sdblock2mem.irq),
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