soc/cores/sdram/settings: simplify modules and fix timing margins computation
This commit is contained in:
Florent Kermarrec
parent
7b3699839e
commit
429f533bd0
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@ -95,8 +95,8 @@ class BaseSoC(SoCSDRAM):
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self.submodules.crg = _CRG(platform)
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = IS42S16160(self.clk_freq)
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),)
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sdram_module = IS42S16160(self.clk_freq, "1:1")
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self.register_sdram(self.sdrphy, "minicon",
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sdram_module.geom_settings, sdram_module.timing_settings)
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@ -93,7 +93,7 @@ class BaseSoC(SoCSDRAM):
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
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sdram_module = MT8JTF12864(self.clk_freq)
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sdram_module = MT8JTF12864(self.clk_freq, "1:4")
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self.register_sdram(self.ddrphy, sdram_controller_type,
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sdram_module.geom_settings, sdram_module.timing_settings)
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@ -76,7 +76,7 @@ class BaseSoC(SoCSDRAM):
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = AS4C16M16(clk_freq)
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sdram_module = AS4C16M16(clk_freq, "1:1")
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self.register_sdram(self.sdrphy, "minicon",
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sdram_module.geom_settings, sdram_module.timing_settings)
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@ -31,7 +31,7 @@ class BaseSoC(SoCSDRAM):
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self.submodules.uart = uart.UART(self.uart_phy)
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if not self.integrated_main_ram_size:
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sdram_module = IS42S16160(self.clk_freq)
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sdram_module = IS42S16160(self.clk_freq, "1:1")
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phy_settings = PhySettings(
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memtype="SDR",
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dfi_databits=1*16,
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@ -27,204 +27,170 @@ TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
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class SDRAMModule:
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def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
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def __init__(self, clk_freq, rate):
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self.clk_freq = clk_freq
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self.memtype = memtype
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self.rate = rate
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self.geom_settings = GeomSettings(
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bankbits=log2_int(geom_settings["nbanks"]),
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rowbits=log2_int(geom_settings["nrows"]),
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colbits=log2_int(geom_settings["ncols"]),
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bankbits=log2_int(self.nbanks),
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rowbits=log2_int(self.nrows),
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colbits=log2_int(self.ncols),
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)
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self.timing_settings = TimingSettings(
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tRP=self.ns(timing_settings["tRP"]),
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tRCD=self.ns(timing_settings["tRCD"]),
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tWR=self.ns(timing_settings["tWR"]),
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tWTR=timing_settings["tWTR"],
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tREFI=self.ns(timing_settings["tREFI"], False),
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tRFC=self.ns(timing_settings["tRFC"])
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tRP=self.ns(self.tRP),
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tRCD=self.ns(self.tRCD),
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tWR=self.ns(self.tWR),
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tWTR=self.tWTR,
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tREFI=self.ns(self.tREFI, False),
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tRFC=self.ns(self.tRFC)
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)
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def ns(self, t, margin=True):
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clk_period_ns = 1000000000/self.clk_freq
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if margin:
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t += clk_period_ns/2
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margins = {
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"1:1" : 0,
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"1:2" : clk_period_ns/2,
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"1:4" : 3*clk_period_ns/4
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}
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t += margins[self.rate]
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return ceil(t/clk_period_ns)
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# SDR
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class IS42S16160(SDRAMModule):
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geom_settings = {
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"nbanks": 4,
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"nrows": 8192,
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"ncols": 512
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}
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# Timings for -7 speedgrade
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timing_settings = {
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"tRP": 20,
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"tRCD": 20,
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"tWR": 20,
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"tWTR": 2,
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"tREFI": 64*1000*1000/8192,
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"tRFC": 70
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
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self.timing_settings)
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memtype = "SDR"
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# geometry
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nbanks = 4
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nrows = 8192
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ncols = 512
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# timings (-7 speedgrade)
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tRP = 20
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tRCD = 20
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tWR = 20
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tWTR = 2
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tREFI = 64*1000*1000/8192
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tRFC = 70
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class MT48LC4M16(SDRAMModule):
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geom_settings = {
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"nbanks": 4,
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"nrows": 4096,
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"ncols": 256
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}
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timing_settings = {
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"tRP": 15,
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"tRCD": 15,
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"tWR": 14,
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"tWTR": 2,
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"tREFI": 64*1000*1000/4096,
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"tRFC": 66
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
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self.timing_settings)
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memtype = "SDR"
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# geometry
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nbanks = 4
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nrows = 4096
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ncols = 256
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# timings (-7 speedgrade)
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tRP = 15
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tRCD = 15
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tWR = 14
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tWTR = 2
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tREFI = 64*1000*1000/4096
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tRFC = 66
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class AS4C16M16(SDRAMModule):
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geom_settings = {
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"nbanks": 4,
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"nrows": 8192,
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"ncols": 512
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}
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# Timings for -6 speedgrade
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timing_settings = {
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"tRP": 18,
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"tRCD": 18,
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"tWR": 12,
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"tWTR": 2,
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"tREFI": 64*1000*1000/8192,
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"tRFC": 60
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
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self.timing_settings)
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memtype = "SDR"
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# geometry
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nbanks = 4
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nrows = 8192
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ncols = 512
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# timings (-6 speedgrade)
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tRP = 18
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tRCD = 18
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tWR = 12
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tWTR = 2
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tREFI = 64*1000*1000/8192
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tRFC = 60
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# DDR
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class MT46V32M16(SDRAMModule):
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geom_settings = {
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"nbanks": 4,
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"nrows": 8192,
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"ncols": 1024
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}
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timing_settings = {
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"tRP": 15,
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"tRCD": 15,
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"tWR": 15,
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"tWTR": 2,
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"tREFI": 64*1000*1000/8192,
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"tRFC": 70
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
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self.timing_settings)
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memtype = "DDR"
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# geometry
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# timings (-6 speedgrade)
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 64*1000*1000/8192
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tRFC = 70
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# LPDDR
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class MT46H32M16(SDRAMModule):
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geom_settings = {
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"nbanks": 4,
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"nrows": 8192,
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"ncols": 1024
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}
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timing_settings = {
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"tRP": 15,
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"tRCD": 15,
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"tWR": 15,
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"tWTR": 2,
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"tREFI": 64*1000*1000/8192,
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"tRFC": 72
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
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self.timing_settings)
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memtype = "LPDDR"
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# geometry
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 64*1000*1000/8192
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tRFC = 72
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# DDR2
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class MT47H128M8(SDRAMModule):
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geom_settings = {
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"nbanks": 8,
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"nrows": 16384,
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"ncols": 1024
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}
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timing_settings = {
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"tRP": 15,
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"tRCD": 15,
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"tWR": 15,
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"tWTR": 2,
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"tREFI": 7800,
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"tRFC": 127.5
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
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self.timing_settings)
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memtype = "DDR2"
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# geometry
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 7800
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tRFC = 127.5
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class P3R1GE4JGF(SDRAMModule):
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geom_settings = {
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"nbanks": 8,
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"nrows": 8192,
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"ncols": 1024
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}
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timing_settings = {
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"tRP": 12.5,
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"tRCD": 12.5,
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"tWR": 15,
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"tWTR": 3,
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"tREFI": 7800,
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"tRFC": 127.5,
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
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self.timing_settings)
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memtype = "DDR2"
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# geometry
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nbanks = 8
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nrows = 8192
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ncols = 1024
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# timings
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tRP = 12.5
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tRCD = 12.5
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tWR = 15
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tWTR = 3
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tREFI = 7800
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tRFC = 127.5
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# DDR3
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class MT8JTF12864(SDRAMModule):
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geom_settings = {
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"nbanks": 8,
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"nrows": 16384,
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"ncols": 1024
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}
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timing_settings = {
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"tRP": 15,
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"tRCD": 15,
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"tWR": 15,
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"tWTR": 2,
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"tREFI": 7800,
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"tRFC": 70
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
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self.timing_settings)
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 2
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tREFI = 7800
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tRFC = 70
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class MT41J128M16(SDRAMModule):
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geom_settings = {
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"nbanks": 8,
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"nrows": 16384,
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"ncols": 1024,
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}
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timing_settings = {
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"tRP": 15,
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"tRCD": 15,
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"tWR": 15,
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"tWTR": 3,
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"tREFI": 64*1000*1000/16384,
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"tRFC": 260,
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}
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def __init__(self, clk_freq):
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SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
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self.timing_settings)
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tWTR = 3
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tREFI = 64*1000*1000/16384
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tRFC = 260
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