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soc/cores/sdram/settings: simplify modules and fix timing margins computation

This commit is contained in:
Florent Kermarrec 2016-04-18 18:22:53 +02:00
parent 7b3699839e
commit 429f533bd0
5 changed files with 130 additions and 164 deletions
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4
litex/boards/targets/de0nano.py
View File

@ -95,8 +95,8 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),)
sdram_module = IS42S16160(self.clk_freq) sdram_module = IS42S16160(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, "minicon", self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings) sdram_module.geom_settings, sdram_module.timing_settings)

2
litex/boards/targets/kc705.py
View File

@ -93,7 +93,7 @@ class BaseSoC(SoCSDRAM):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram")) self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq) sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type, self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings) sdram_module.geom_settings, sdram_module.timing_settings)

2
litex/boards/targets/minispartan6.py
View File

@ -76,7 +76,7 @@ class BaseSoC(SoCSDRAM):
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C16M16(clk_freq) sdram_module = AS4C16M16(clk_freq, "1:1")
self.register_sdram(self.sdrphy, "minicon", self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings) sdram_module.geom_settings, sdram_module.timing_settings)

2
litex/boards/targets/sim.py
View File

@ -31,7 +31,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.uart = uart.UART(self.uart_phy) self.submodules.uart = uart.UART(self.uart_phy)
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
sdram_module = IS42S16160(self.clk_freq) sdram_module = IS42S16160(self.clk_freq, "1:1")
phy_settings = PhySettings( phy_settings = PhySettings(
memtype="SDR", memtype="SDR",
dfi_databits=1*16, dfi_databits=1*16,

284
litex/soc/cores/sdram/settings.py
View File

@ -27,204 +27,170 @@ TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
class SDRAMModule: class SDRAMModule:
def __init__(self, clk_freq, memtype, geom_settings, timing_settings): def __init__(self, clk_freq, rate):
self.clk_freq = clk_freq self.clk_freq = clk_freq
self.memtype = memtype self.rate = rate
self.geom_settings = GeomSettings( self.geom_settings = GeomSettings(
bankbits=log2_int(geom_settings["nbanks"]), bankbits=log2_int(self.nbanks),
rowbits=log2_int(geom_settings["nrows"]), rowbits=log2_int(self.nrows),
colbits=log2_int(geom_settings["ncols"]), colbits=log2_int(self.ncols),
) )
self.timing_settings = TimingSettings( self.timing_settings = TimingSettings(
tRP=self.ns(timing_settings["tRP"]), tRP=self.ns(self.tRP),
tRCD=self.ns(timing_settings["tRCD"]), tRCD=self.ns(self.tRCD),
tWR=self.ns(timing_settings["tWR"]), tWR=self.ns(self.tWR),
tWTR=timing_settings["tWTR"], tWTR=self.tWTR,
tREFI=self.ns(timing_settings["tREFI"], False), tREFI=self.ns(self.tREFI, False),
tRFC=self.ns(timing_settings["tRFC"]) tRFC=self.ns(self.tRFC)
) )
def ns(self, t, margin=True): def ns(self, t, margin=True):
clk_period_ns = 1000000000/self.clk_freq clk_period_ns = 1000000000/self.clk_freq
if margin: if margin:
t += clk_period_ns/2 margins = {
"1:1" : 0,
"1:2" : clk_period_ns/2,
"1:4" : 3*clk_period_ns/4
}
t += margins[self.rate]
return ceil(t/clk_period_ns) return ceil(t/clk_period_ns)
# SDR # SDR
class IS42S16160(SDRAMModule): class IS42S16160(SDRAMModule):
geom_settings = { memtype = "SDR"
"nbanks": 4, # geometry
"nrows": 8192, nbanks = 4
"ncols": 512 nrows = 8192
} ncols = 512
# Timings for -7 speedgrade # timings (-7 speedgrade)
timing_settings = { tRP = 20
"tRP": 20, tRCD = 20
"tRCD": 20, tWR = 20
"tWR": 20, tWTR = 2
"tWTR": 2, tREFI = 64*1000*1000/8192
"tREFI": 64*1000*1000/8192, tRFC = 70
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)
class MT48LC4M16(SDRAMModule): class MT48LC4M16(SDRAMModule):
geom_settings = { memtype = "SDR"
"nbanks": 4, # geometry
"nrows": 4096, nbanks = 4
"ncols": 256 nrows = 4096
} ncols = 256
timing_settings = { # timings (-7 speedgrade)
"tRP": 15, tRP = 15
"tRCD": 15, tRCD = 15
"tWR": 14, tWR = 14
"tWTR": 2, tWTR = 2
"tREFI": 64*1000*1000/4096, tREFI = 64*1000*1000/4096
"tRFC": 66 tRFC = 66
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)
class AS4C16M16(SDRAMModule): class AS4C16M16(SDRAMModule):
geom_settings = { memtype = "SDR"
"nbanks": 4, # geometry
"nrows": 8192, nbanks = 4
"ncols": 512 nrows = 8192
} ncols = 512
# Timings for -6 speedgrade # timings (-6 speedgrade)
timing_settings = { tRP = 18
"tRP": 18, tRCD = 18
"tRCD": 18, tWR = 12
"tWR": 12, tWTR = 2
"tWTR": 2, tREFI = 64*1000*1000/8192
"tREFI": 64*1000*1000/8192, tRFC = 60
"tRFC": 60
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)
# DDR # DDR
class MT46V32M16(SDRAMModule): class MT46V32M16(SDRAMModule):
geom_settings = { memtype = "DDR"
"nbanks": 4, # geometry
"nrows": 8192, nbanks = 4
"ncols": 1024 nrows = 8192
} ncols = 1024
timing_settings = { # timings (-6 speedgrade)
"tRP": 15, tRP = 15
"tRCD": 15, tRCD = 15
"tWR": 15, tWR = 15
"tWTR": 2, tWTR = 2
"tREFI": 64*1000*1000/8192, tREFI = 64*1000*1000/8192
"tRFC": 70 tRFC = 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
self.timing_settings)
# LPDDR # LPDDR
class MT46H32M16(SDRAMModule): class MT46H32M16(SDRAMModule):
geom_settings = { memtype = "LPDDR"
"nbanks": 4, # geometry
"nrows": 8192, nbanks = 4
"ncols": 1024 nrows = 8192
} ncols = 1024
timing_settings = { # timings
"tRP": 15, tRP = 15
"tRCD": 15, tRCD = 15
"tWR": 15, tWR = 15
"tWTR": 2, tWTR = 2
"tREFI": 64*1000*1000/8192, tREFI = 64*1000*1000/8192
"tRFC": 72 tRFC = 72
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
self.timing_settings)
# DDR2 # DDR2
class MT47H128M8(SDRAMModule): class MT47H128M8(SDRAMModule):
geom_settings = { memtype = "DDR2"
"nbanks": 8, # geometry
"nrows": 16384, nbanks = 8
"ncols": 1024 nrows = 16384
} ncols = 1024
timing_settings = { # timings
"tRP": 15, tRP = 15
"tRCD": 15, tRCD = 15
"tWR": 15, tWR = 15
"tWTR": 2, tWTR = 2
"tREFI": 7800, tREFI = 7800
"tRFC": 127.5 tRFC = 127.5
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
self.timing_settings)
class P3R1GE4JGF(SDRAMModule): class P3R1GE4JGF(SDRAMModule):
geom_settings = { memtype = "DDR2"
"nbanks": 8, # geometry
"nrows": 8192, nbanks = 8
"ncols": 1024 nrows = 8192
} ncols = 1024
timing_settings = { # timings
"tRP": 12.5, tRP = 12.5
"tRCD": 12.5, tRCD = 12.5
"tWR": 15, tWR = 15
"tWTR": 3, tWTR = 3
"tREFI": 7800, tREFI = 7800
"tRFC": 127.5, tRFC = 127.5
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
self.timing_settings)
# DDR3 # DDR3
class MT8JTF12864(SDRAMModule): class MT8JTF12864(SDRAMModule):
geom_settings = { memtype = "DDR3"
"nbanks": 8, # geometry
"nrows": 16384, nbanks = 8
"ncols": 1024 nrows = 16384
} ncols = 1024
timing_settings = { # timings
"tRP": 15, tRP = 15
"tRCD": 15, tRCD = 15
"tWR": 15, tWR = 15
"tWTR": 2, tWTR = 2
"tREFI": 7800, tREFI = 7800
"tRFC": 70 tRFC = 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
self.timing_settings)
class MT41J128M16(SDRAMModule): class MT41J128M16(SDRAMModule):
geom_settings = { memtype = "DDR3"
"nbanks": 8, # geometry
"nrows": 16384, nbanks = 8
"ncols": 1024, nrows = 16384
} ncols = 1024
timing_settings = { # timings
"tRP": 15, tRP = 15
"tRCD": 15, tRCD = 15
"tWR": 15, tWR = 15
"tWTR": 3, tWTR = 3
"tREFI": 64*1000*1000/16384, tREFI = 64*1000*1000/16384
"tRFC": 260, tRFC = 260
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
self.timing_settings)