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SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args.

This commit is contained in:
Florent Kermarrec 2020-01-14 09:23:30 +01:00
parent 4050e60834
commit 42efa99826
1 changed files with 6 additions and 4 deletions
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10
litex/soc/integration/soc_core.py
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@ -85,9 +85,9 @@ class SoCCore(Module):
# CPU parameters # CPU parameters
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
# ROM parameters # ROM parameters
integrated_rom_size=0x8000, integrated_rom_init=[], integrated_rom_size=0, integrated_rom_init=[],
# SRAM parameters # SRAM parameters
integrated_sram_size=0x1000, integrated_sram_init=[], integrated_sram_size=0, integrated_sram_init=[],
# MAIN_RAM parameters # MAIN_RAM parameters
integrated_main_ram_size=0, integrated_main_ram_init=[], integrated_main_ram_size=0, integrated_main_ram_init=[],
# CSR parameters # CSR parameters
@ -139,8 +139,10 @@ class SoCCore(Module):
self.integrated_rom_size = integrated_rom_size self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != [] self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size if cpu_type is not None and integrated_sram_size == 0:
self.integrated_main_ram_size = integrated_main_ram_size integrated_sram_size = 0x1000
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 16, 32] assert csr_data_width in [8, 16, 32]
self.csr_data_width = csr_data_width self.csr_data_width = csr_data_width