Merge pull request #2018 from motec-research/add_i2c_master
Add i2c master
This commit is contained in:
enjoy-digital
GitHub
commit
4301293b21
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#
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# This file is part of MiSoC and has been adapted/modified for Litex.
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#
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# Copyright 2007-2023 / M-Labs Ltd
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# Copyright 2012-2015 / Enjoy-Digital
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# Copyright from Misoc LICENCE file added above
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#
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# Copyright 2023 Andrew Dennison <andrew@motec.com.au>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr_eventmanager import *
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# I2C-----------------------------------------------------------------------------------------------
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__all__ = [
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"I2CMaster",
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"I2C_XFER_ADDR", "I2C_CONFIG_ADDR",
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"I2C_ACK", "I2C_READ", "I2C_WRITE", "I2C_STOP", "I2C_START", "I2C_IDLE",
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]
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class I2CClockGen(LiteXModule):
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def __init__(self, width):
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self.load = Signal(width)
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self.clk2x = Signal()
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cnt = Signal.like(self.load)
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self.comb += [
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self.clk2x.eq(cnt == 0),
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]
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self.sync += [
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If(self.clk2x,
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cnt.eq(self.load),
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).Else(
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cnt.eq(cnt - 1),
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),
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]
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class I2CMasterMachine(LiteXModule):
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def __init__(self, clock_width):
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self.scl_o = Signal(reset=1)
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self.sda_o = Signal(reset=1)
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self.sda_i = Signal()
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self.cg = CEInserter()(I2CClockGen(clock_width))
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self.idle = Signal()
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self.start = Signal()
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self.stop = Signal()
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self.write = Signal()
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self.read = Signal()
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self.ack = Signal()
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self.data = Signal(8)
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###
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busy = Signal()
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bits = Signal(4)
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fsm = CEInserter()(FSM("IDLE"))
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self.fsm = fsm
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fsm.act("IDLE",
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# Valid combinations (lowest to highest priority):
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# stop: lowest priority
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# read (& optional stop with automatic NACK)
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# write (& optional stop)
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# start (indicates start or restart)
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# start & write (& optional stop)
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# start & write & read (& optional stop)
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# lowest priority
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# *** TODO: support compound commands with I2CMaster ***
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If(self.stop & ~self.scl_o,
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# stop is only valid after an ACK
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NextState("STOP0"),
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),
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If(self.read,
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# post decrement so read first bit and shift in 7
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NextValue(bits, 8-1),
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NextState("READ0"),
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),
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If(self.write,
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NextValue(bits, 8),
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NextState("WRITE0"),
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),
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# start could be requesting a restart
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If(self.start,
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NextState("RESTART0"),
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),
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# highest priority: start only if scl is high
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If(self.start & self.scl_o,
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NextState("START0"),
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),
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)
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fsm.act("START0",
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# Always entered with scl_o = 1
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NextValue(self.sda_o, 0),
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NextState("IDLE"))
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fsm.act("RESTART0",
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# Only entered from IDLE with scl_o = 0
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NextValue(self.sda_o, 1),
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NextState("RESTART1"))
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fsm.act("RESTART1",
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NextValue(self.scl_o, 1),
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NextState("START0"))
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fsm.act("STOP0",
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# Only entered from IDLE with scl_o = 0
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NextValue(self.sda_o, 0),
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NextState("STOP1"))
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fsm.act("STOP1",
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NextValue(self.scl_o, 1),
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NextState("STOP2"))
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fsm.act("STOP2",
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NextValue(self.sda_o, 1),
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NextState("IDLE"))
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fsm.act("WRITE0",
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NextValue(self.scl_o, 0),
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If(bits == 0,
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NextValue(self.sda_o, 1),
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NextState("READACK0"),
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).Else(
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NextValue(self.sda_o, self.data[7]),
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NextState("WRITE1"),
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)
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)
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fsm.act("WRITE1",
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NextValue(self.scl_o, 1),
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NextValue(self.data[1:], self.data[:-1]),
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NextValue(bits, bits - 1),
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NextState("WRITE0"),
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)
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fsm.act("READACK0",
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NextValue(self.scl_o, 1),
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NextState("READACK1"),
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)
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fsm.act("READACK1",
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# ACK => IDLE always with scl_o = 0
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NextValue(self.scl_o, 0),
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NextValue(self.ack, ~self.sda_i),
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NextState("IDLE")
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)
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fsm.act("READ0",
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# ACK => IDLE => READ0 always with scl_o = 0
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NextValue(self.scl_o, 1),
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NextState("READ1"),
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)
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fsm.act("READ1",
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NextValue(self.data[0], self.sda_i),
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NextValue(self.scl_o, 0),
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If(bits == 0,
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NextValue(self.sda_o, ~self.ack),
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NextState("WRITEACK0"),
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).Else(
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#NextValue(self.sda_o, 1), must already be high
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NextState("READ2"),
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)
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)
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fsm.act("READ2",
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NextValue(self.scl_o, 1),
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NextValue(self.data[1:], self.data[:-1]),
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NextValue(bits, bits - 1),
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NextState("READ1"),
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)
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fsm.act("WRITEACK0",
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NextValue(self.scl_o, 1),
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NextState("WRITEACK1"),
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)
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fsm.act("WRITEACK1",
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# ACK => IDLE always with scl_o = 0
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NextValue(self.scl_o, 0),
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NextValue(self.sda_o, 1),
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NextState("IDLE")
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)
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run = Signal()
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self.comb += [
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run.eq(self.start | self.stop | self.write | self.read),
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self.idle.eq(~run & fsm.ongoing("IDLE")),
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self.cg.ce.eq(~self.idle),
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fsm.ce.eq(run | self.cg.clk2x),
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]
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# Registers:
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# config = Record([
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# ("div", 20),
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# ])
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# xfer = Record([
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# ("data", 8),
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# ("ack", 1),
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# ("read", 1),
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# ("write", 1),
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# ("start", 1),
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# ("stop", 1),
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# ("idle", 1),
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# ])
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class I2CMaster(LiteXModule):
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def __init__(self, pads, bus=None):
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if bus is None:
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bus = wishbone.Interface(data_width=32)
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self.bus = bus
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###
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# Wishbone
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self.i2c = i2c = I2CMasterMachine(
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clock_width=20)
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self.sync += [
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# read
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If(bus.adr[0],
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bus.dat_r.eq(i2c.cg.load),
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).Else(
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bus.dat_r.eq(Cat(i2c.data, i2c.ack, C(0, 4), i2c.idle)),
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),
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# write
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i2c.read.eq(0),
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i2c.write.eq(0),
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i2c.start.eq(0),
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i2c.stop.eq(0),
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bus.ack.eq(0),
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If(bus.cyc & bus.stb & ~bus.ack,
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bus.ack.eq(1),
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If(bus.we,
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If(bus.adr[0],
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i2c.cg.load.eq(bus.dat_w),
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).Else(
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i2c.data.eq(bus.dat_w[0:8]),
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i2c.ack.eq(bus.dat_w[8]),
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i2c.read.eq(bus.dat_w[9]),
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i2c.write.eq(bus.dat_w[10]),
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i2c.start.eq(bus.dat_w[11]),
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i2c.stop.eq(bus.dat_w[12]),
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)
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)
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)
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]
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# I/O
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self.scl_t = TSTriple()
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self.scl_tristate = self.scl_t.get_tristate(pads.scl)
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self.comb += [
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self.scl_t.oe.eq(~i2c.scl_o),
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self.scl_t.o.eq(0),
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]
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self.sda_t = TSTriple()
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self.sda_tristate = self.sda_t.get_tristate(pads.sda)
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self.scl_i_n = Signal() # previous scl_t.i
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self.sda_oe_n = Signal() # previous sda_t.oe
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self.sync += [
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self.scl_i_n.eq(self.scl_t.i),
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self.sda_oe_n.eq(self.sda_t.oe),
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]
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self.comb += [
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self.sda_t.oe.eq(self.sda_oe_n),
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# only change SDA when SCL is stable
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If(self.scl_i_n == i2c.scl_o,
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self.sda_t.oe.eq(~i2c.sda_o),
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),
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self.sda_t.o.eq(0),
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i2c.sda_i.eq(self.sda_t.i),
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]
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# Event Manager.
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self.ev = EventManager()
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self.ev.idle = EventSourceProcess(edge="rising")
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self.ev.finalize()
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self.comb += self.ev.idle.trigger.eq(i2c.idle)
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I2C_XFER_ADDR, I2C_CONFIG_ADDR = range(2)
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(
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I2C_ACK,
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I2C_READ,
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I2C_WRITE,
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I2C_START,
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I2C_STOP,
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I2C_IDLE,
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) = (1 << i for i in range(8, 14))
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@ -0,0 +1,226 @@
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#!/usr/bin/env python3
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#
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# This file is part of MiSoC and has been adapted/modified for Litex.
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#
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# Copyright 2007-2023 / M-Labs Ltd
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# Copyright 2012-2015 / Enjoy-Digital
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# Copyright from Misoc LICENCE file added above
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#
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# Copyright 2023 Andrew Dennison <andrew@motec.com.au>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from migen.fhdl.specials import Tristate
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from litex.soc.cores.i2c import *
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class _MockPads:
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def __init__(self):
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self.scl = Signal()
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self.sda = Signal()
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class _MockTristateImpl(Module):
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def __init__(self, t):
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t.i_mock = Signal(reset=True)
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self.comb += [
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If(t.oe,
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t.target.eq(t.o),
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t.i.eq(t.o),
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).Else(
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t.target.eq(t.i_mock),
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t.i.eq(t.i_mock),
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),
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]
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class _MockTristate:
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"""A mock `Tristate` for simulation
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This simulation ensures the TriState input (_i) tracks the output (_o) when output enable
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(_oe) = 1. A new i_mock `Signal` is added - this can be written to in the simulation to represent
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input from the external device.
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Example usage:
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class TestMyModule(unittest.TestCase):
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def test_mymodule(self):
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dut = MyModule()
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io = Signal()
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dut.io_t = TSTriple()
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self.io_tristate = self.io_t.get_tristate(io)
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dut.comb += [
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dut.io_t.oe.eq(signal_for_oe),
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dut.io_t.o.eq(signal_for_o),
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signal_for_i.eq(dut.io_t.i),
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]
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def generator()
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yield dut.io_tristate.i_mock.eq(some_value)
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if (yield dut.io_t.oe):
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self.assertEqual((yield dut.scl_t.i), (yield dut.io_t.o))
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else:
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self.assertEqual((yield dut.scl_t.i), some_value)
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"""
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@staticmethod
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def lower(t):
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return _MockTristateImpl(t)
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class TestI2C(unittest.TestCase):
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def test_i2c(self):
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pads = _MockPads()
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dut = I2CMaster(pads)
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def check_trans(scl, sda, msg=""):
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scl, sda = int(scl), int(sda)
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scl_init, sda_init = (yield dut.scl_t.i), (yield dut.sda_t.i)
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timeout = 0
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while True:
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scl_now, sda_now = (yield dut.scl_t.i), (yield dut.sda_t.i)
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if scl_now == scl and sda_now == sda:
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return
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timeout += 1
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self.assertLess(timeout, 20,
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f"\n*** {msg} timeout. Waiting for: " +
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f"scl:{scl_now} checking:{scl_init}=>{scl} " +
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f"sda:{sda_now} checking:{sda_init}=>{sda} ***"
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)
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yield
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def wait_idle(do=lambda: ()):
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timeout = 0
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while True:
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timeout += 1
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self.assertLess(timeout, 20)
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idle = ((yield from dut.bus.read(I2C_XFER_ADDR)) & I2C_IDLE) != 0
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if idle:
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return
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yield
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def write_bit(value):
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# print(f"write_bit:{value}")
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yield from check_trans(scl=False, sda=value)
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yield from check_trans(scl=True, sda=value)
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def write_ack(value):
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# print(f"write_ack:{value}")
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yield from check_trans(scl=False, sda=not value)
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yield from check_trans(scl=True, sda=not value)
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yield from wait_idle()
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def read_bit(value):
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print(f"read_bit:{value}")
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yield dut.sda_tristate.i_mock.eq(value)
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yield from check_trans(scl=True, sda=value)
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yield from check_trans(scl=False, sda=value)
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yield dut.sda_tristate.i_mock.eq(True)
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def read_ack(value):
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#print(f"read_ack:{value}")
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yield from check_trans(scl=False, sda=True)
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yield dut.sda_tristate.i_mock.eq(not value)
|
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yield from check_trans(scl=True, sda=not value)
|
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yield from wait_idle()
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yield dut.sda_tristate.i_mock.eq(True)
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ack = ((yield from dut.bus.read(I2C_XFER_ADDR)) & I2C_ACK) != 0
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self.assertEqual(ack, value)
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|
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def i2c_restart():
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yield from check_trans(scl=False, sda=True, msg="checking restart precondition")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START)
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yield from check_trans(scl=False, sda=True, msg="checking restart0")
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yield from check_trans(scl=True, sda=True, msg="checking restart1")
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yield from check_trans(scl=True, sda=False, msg="checking start0")
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yield from wait_idle()
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def i2c_start():
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yield from check_trans(scl=True, sda=True, msg="checking start precondition")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START)
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yield from check_trans(scl=True, sda=False, msg="checking start0")
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yield from wait_idle()
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def i2c_stop():
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yield from check_trans(scl=False, sda=True, msg="checking stop after read or write")
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_STOP)
|
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yield from check_trans(scl=False, sda=False, msg="checking STOP0")
|
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yield from check_trans(scl=True, sda=False, msg="checking STOP1")
|
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yield from check_trans(scl=True, sda=True, msg="checking STOP2")
|
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yield from wait_idle()
|
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def i2c_write(value, ack=True):
|
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value = int(value)
|
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test_bin = "{0:08b}".format(value)
|
||||
# print(f"I2C_WRITE | {hex(value)}:0x{test_bin}")
|
||||
yield from dut.bus.write(I2C_XFER_ADDR, I2C_WRITE | value)
|
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for i in list(test_bin):
|
||||
yield from write_bit(int(i))
|
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yield from read_ack(True)
|
||||
|
||||
def i2c_read(value, ack=True):
|
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value = int(value)
|
||||
test_bin = "{0:08b}".format(value)
|
||||
print(f"I2C_READ | {hex(value)}:0x{test_bin}")
|
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_READ | (I2C_ACK if ack else 0))
|
||||
for i in list(test_bin):
|
||||
yield from read_bit(int(i))
|
||||
yield dut.sda_tristate.i_mock.eq(True)
|
||||
data = (yield from dut.bus.read(I2C_XFER_ADDR)) & 0xFF
|
||||
self.assertEqual(data, value)
|
||||
yield from write_ack(ack)
|
||||
|
||||
def check():
|
||||
yield from dut.bus.write(I2C_CONFIG_ADDR, 4)
|
||||
data = (yield from dut.bus.read(I2C_CONFIG_ADDR)) & 0xFF
|
||||
self.assertEqual(data, 4)
|
||||
|
||||
print("write 1 byte 0x18 to address 0x41")
|
||||
yield from i2c_start()
|
||||
yield from i2c_write(0x41 << 1 | 0)
|
||||
yield from i2c_write(0x18, ack=False)
|
||||
yield from i2c_stop()
|
||||
|
||||
print("read 1 byte from address 0x41")
|
||||
yield from i2c_start()
|
||||
yield from i2c_write(0x41 << 1 | 1)
|
||||
yield from i2c_read(0x18, ack=False)
|
||||
|
||||
print("write 2 bytes 0x10 0x00 to address 0x11")
|
||||
yield from i2c_restart()
|
||||
yield from i2c_write(0x11 << 1 | 0)
|
||||
yield from i2c_write(0x10, ack=True)
|
||||
yield from i2c_write(0x00, ack=False)
|
||||
yield from i2c_stop()
|
||||
|
||||
print("read 1 byte from address 0x11")
|
||||
yield from i2c_start()
|
||||
yield from i2c_write(0x11 << 1 | 1)
|
||||
yield from i2c_read(0x81, ack=False)
|
||||
|
||||
print("read 2 bytes from address 0x55")
|
||||
yield from i2c_restart()
|
||||
yield from i2c_write(0x55 << 1 | 1)
|
||||
yield from i2c_read(0xDE, ack=True)
|
||||
yield from i2c_read(0xAD, ack=False)
|
||||
yield from i2c_stop()
|
||||
|
||||
clocks = {
|
||||
"sys": 10,
|
||||
"async": (10, 3),
|
||||
}
|
||||
generators = {
|
||||
"sys": [
|
||||
check(),
|
||||
],
|
||||
}
|
||||
run_simulation(dut, generators, clocks, special_overrides={Tristate: _MockTristate}, vcd_name="i2c.vcd")
|
||||
|
||||
if __name__ == "__main__":
|
||||
unittest.main()
|
||||
Loading…
Reference in New Issue