bios/sdram: update kuddrphy initialization procedure
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90dcd45f0b
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4324c6f666
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@ -222,11 +222,17 @@ void sdrwloff(void)
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static int write_level(int *delay, int *high_skew)
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{
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int i;
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int i, j;
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int dq_address;
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unsigned char dq;
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int err_ddrphy_wdly;
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int ok;
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err_ddrphy_wdly = ERR_DDRPHY_DELAY;
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#ifdef CSR_DDRPHY_WDLY_DQS_TAPS_ADDR
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printf("Write leveling dqs taps offset: %d\n", ddrphy_wdly_dqs_taps_read());
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err_ddrphy_wdly = ERR_DDRPHY_DELAY - ddrphy_wdly_dqs_taps_read();
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#endif
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printf("Write leveling: ");
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sdrwlon();
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@ -236,6 +242,10 @@ static int write_level(int *delay, int *high_skew)
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ddrphy_dly_sel_write(1 << i);
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ddrphy_wdly_dq_rst_write(1);
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ddrphy_wdly_dqs_rst_write(1);
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#ifdef CSR_DDRPHY_WDLY_DQS_TAPS_ADDR
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for(j=0; j<ddrphy_wdly_dqs_taps_read(); j++)
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ddrphy_wdly_dqs_inc_write(1);
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#endif
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delay[i] = 0;
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@ -250,7 +260,7 @@ static int write_level(int *delay, int *high_skew)
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high_skew[i] = 1;
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while(dq != 0) {
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delay[i]++;
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if(delay[i] >= ERR_DDRPHY_DELAY)
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if(delay[i] >= err_ddrphy_wdly)
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break;
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ddrphy_wdly_dq_inc_write(1);
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ddrphy_wdly_dqs_inc_write(1);
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@ -263,7 +273,7 @@ static int write_level(int *delay, int *high_skew)
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while(dq == 0) {
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delay[i]++;
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if(delay[i] >= ERR_DDRPHY_DELAY)
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if(delay[i] >= err_ddrphy_wdly)
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break;
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ddrphy_wdly_dq_inc_write(1);
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ddrphy_wdly_dqs_inc_write(1);
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@ -278,7 +288,7 @@ static int write_level(int *delay, int *high_skew)
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ok = 1;
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for(i=DFII_PIX_DATA_SIZE/2-1;i>=0;i--) {
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printf("%2d%c ", delay[i], high_skew[i] ? '*' : ' ');
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if(delay[i] >= ERR_DDRPHY_DELAY)
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if(delay[i] >= err_ddrphy_wdly)
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ok = 0;
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}
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@ -653,7 +663,13 @@ int sdrinit(void)
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init_sequence();
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#ifdef CSR_DDRPHY_BASE
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#if CSR_DDRPHY_EN_VTC_ADDR
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ddrphy_en_vtc_write(0);
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#endif
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sdrlevel();
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#if CSR_DDRPHY_EN_VTC_ADDR
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ddrphy_en_vtc_write(1);
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#endif
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#endif
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sdram_dfii_control_write(DFII_CONTROL_SEL);
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if(!memtest())
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