integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone).

litex/soc/integration/soc.py

@@ -803,8 +803,8 @@ class SoC(Module):
             self.bus.regions[name]))
         setattr(self.submodules, name, ram)
 
-    def add_rom(self, name, origin, size, contents=[]):
-        self.add_ram(name, origin, size, contents, mode="r")
+    def add_rom(self, name, origin, size, contents=[], mode="r"):
+        self.add_ram(name, origin, size, contents, mode=mode)
 
     def add_csr_bridge(self, origin, register=False):
         csr_bridge_cls = {
@@ -1170,10 +1170,10 @@ class LiteXSoC(SoC):
                     if spd_byte < len(module._spd_data):
                         mem[i] |= module._spd_data[spd_byte]
             self.add_rom(
-                name="spd",
-                origin=self.mem_map.get("spd", None),
-                size=len(module._spd_data),
-                contents=mem,
+                name     = "spd",
+                origin   = self.mem_map.get("spd", None),
+                size     = len(module._spd_data),
+                contents = mem,
             )
 
         if not with_soc_interconnect: return

litex/soc/integration/soc_core.py

@@ -71,6 +71,7 @@ class SoCCore(LiteXSoC):
         cpu_cls                  = None,
         # ROM parameters
         integrated_rom_size      = 0,
+        integrated_rom_mode      = "r",
         integrated_rom_init      = [],
         # SRAM parameters
         integrated_sram_size     = 0x2000,
@@ -161,7 +162,7 @@ class SoCCore(LiteXSoC):
 
         # Add integrated ROM
         if integrated_rom_size:
-            self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init)
+            self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init, integrated_rom_mode)
 
         # Add integrated SRAM
         if integrated_sram_size: